Process to define N/PMOS poly patterns

Details Process to define N/PMOS poly patterns Process to define N/PMOS poly patterns

2002-02-21

2003-05-20

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S532000

Reexamination Certificate

active

06566184

ABSTRACT:

BACKGROUND OF THE INVENTION
For device process concerns, sometimes N metal-oxide semiconductor (MOS) and PMOS implants were required before defining polysilicon (poly) lines to avoid interfering with subsequent NLDD implants as in 0.10 &mgr;m technology. The poly line etch process has to be fine tuned when using pre-doped poly film. However, when using pre-doped poly film it is very difficult to get a good poly line pattern, especially for pre-doped poly films having different implant dosages and implant species. Further, since the etch bias is different between the NMOS and PMOS portions of the pre-doped poly film, a separate NMOS pre-doped poly etch and a separate PMOS pre-doped poly etch are required for proper process control.
U.S. Pat. No. 6,171,889 B1 to Iwamatsu et al. describes an N & P MOS process where the poly is N and P doped after deposition and the N poly is doped before patterning.
U.S. Pat. No. 6,258,641 B1 to Wong et al. describes an N/PMOS poly patterning process using a triple well method.
U.S. Pat. No. 6,191,044 B1 to Yu et al. describes an NMOS and PMOS process using a controlled poly gate profile.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide a improved process of forming NMOS and PMOS poly structures.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided and an undoped polysilicon layer is formed over the substrate. The undoped polysilicon layer is patterned to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area. The at least one undoped polysilicon structure within the N area is masked, leaving exposed an upper portion of the other at least one undoped polysilicon structure within the P area. The exposed at least one undoped polysilicon structure within the P area is doped to form a P-doped polysilicon structure. An upper portion of the masked at least one undoped polysilicon structure within the N area is unmasked and exposed, and the P-doped polysilicon structure is masked. The exposed at least one undoped polysilicon structure within the N area is doped to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.


REFERENCES:
patent: 6103603 (2000-08-01), Han
patent: 6171889 (2001-01-01), Iwamatsu et al.
patent: 6191044 (2001-02-01), Yu et al.
patent: 6258641 (2001-07-01), Wong et al.
patent: 6391704 (2002-05-01), Hong et al.
patent: 6399432 (2002-06-01), Zheng et al.

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