Process technology architecture of embedded DRAM

Details Process technology architecture of embedded DRAM Process technology architecture of embedded DRAM

1998-11-19

2000-10-24

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438239, H01L 218234, H01L 218242, H01L 21336

Patent

active

061366382

ABSTRACT:
Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the voltage levels created by the logic core. If the gate oxide has a thickness that is equal to the gate oxide thickness of the peripheral circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by peripheral circuits, and signal provided by the bit line voltage generator has voltage levels equal to those provided by logic circuits within the logic core. If the gate oxide has a thickness that is equal to the thickness of the gate oxide of the logic circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by the logic circuits, and the bit line voltage generator has voltage levels equal to those provided by the logic circuits.

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