Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-05-30
2008-11-04
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S306000, C257SE21170, C257SE21304, C257SE21546, C257SE21586, C257SE21646, C257SE21647, C257SE21651
Reexamination Certificate
active
07446366
ABSTRACT:
A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
REFERENCES:
patent: 4454646 (1984-06-01), Joy et al.
patent: 4473598 (1984-09-01), Ephrath et al.
patent: 4526631 (1985-07-01), Silvestri et al.
patent: 6251722 (2001-06-01), Wei et al.
patent: 6352593 (2002-03-01), Brors et al.
patent: 7109097 (2006-09-01), Paranjpe et al.
patent: 7265023 (2007-09-01), Haupt et al.
patent: 7265025 (2007-09-01), Temmler et al.
patent: 2002/0167045 (2002-11-01), Short
patent: 2003/0049372 (2003-03-01), Cook et al.
patent: 2004/0043580 (2004-03-01), Rueger et al.
PCT Partial International Search Report for International Application No. PCT/US05/44985; International Filing Date Dec. 13, 2005 (APPM/9621PCT).
Clemens Heitzinger et al. “Simulation of Arsenic In Situ Doping with Polysilicon CVD and Its Application to High Aspect Ratio Trenchee,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Mar. 2003 vol. 22(3): 285-292.
Nag Somnath
Paranjpe Ajit
Applied Materials Inc.
Nhu David
Patterson & Sheridan LLP
LandOfFree
Process sequence for doped silicon fill of deep trenches does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process sequence for doped silicon fill of deep trenches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process sequence for doped silicon fill of deep trenches will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4021270