Process of manufacturing Trench gate semiconductor device...

Details Process of manufacturing Trench gate semiconductor device... Process of manufacturing Trench gate semiconductor device...

1999-05-25

2001-09-18

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000, C438S274000, C257S330000

Reexamination Certificate

active

06291298

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices having a gate electrode that is embedded in a trench and in particular to structures and methods of protecting such devices against damage to the gate oxide layer when the devices are subjected to high voltage differences while in an off condition. The invention particularly relates to trench MOSFETs.
BACKGROUND OF THE INVENTION
There is a class of semiconductor devices in which a gate electrode is formed in a trench that extends from the surface of a semiconductor chip. One example is a trench-gated MOSFET, and other examples include insulated gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs) and accumulation-mode field-effect transistors (ACCUFETs). All of these devices share the common characteristic of a trench structure where thie bottom of the trench for some reason can be exposed to high electric fields or where the bottom of the trench might form a parasitic capacitor including the gate electrode and the semiconductor material surrounding the trench.
FIGS. 1 through 10
show cross-sectional views and characteristics of known trench-gated devices.
FIG. 1
shows a trench-gated MOSFET
100
having a top metal layer
102
, a gate
104
formed in a trench
106
and separated from an epitaxial silicon layer
108
by a gate oxide layer
110
. MOSFET
100
also includes an N+source region
112
and a P−body
114
. The drain of MOSFET
100
includes the N−epi layer
108
and an N+substrate
116
. A deep P+region
118
is created under P−body
114
, as suggested in U.S. Pat. No. 5,072,266 to Bulucea et al. The PN junction between deep P+region
118
and N−epi layer
108
forms a voltage-clamping diode
117
where avalanche breakdown normally occurs. A P+body contact region
119
forms a contact between metal layer
102
and P−body
114
. The gate, which is typically formed of polysilicon, is protected from the metal layer
102
by an oxide layer
120
that is above the gate
104
and that is patterned with a feature that does not correspond to the trench itself, typically a contact mask.
As shown, gate oxide layer
110
consists of a uniform thin layer of oxide along the three sides of the polysilicon gate
104
. That is, the portions of gate oxide layer
110
on the sidewalls of the trench and also the curved and linear portions of the gate oxide layer
110
at the bottom of the trench (except for some stress-related and etch-related changes in the oxide thickness that occur at the trench bottom) are generally of a uniform thickness in the range of, for example, 150 Å to 1,200 Å.
There are many variations of this general type of MOSFET. For example,
FIG. 2
shows a MOSFET
130
which is generally similar to MOSFEFT
100
but does not include a deep P+region
118
. The gate of MOSFEFT
130
protrudes slightly through P−body
132
because the depth of P−body
132
and the depth of the trench
134
are determined in two unrelated processes. Thus, in vertical devices there is no guarantee of the net overlap of the polysilicon gate into the drain region. It turns out that this variation affects the operation of the device and may affect its reliability as well. Also, in
FIG. 2
there is no additional diode formed by the deep P+region
118
to clamp the voltage, so breakdown can occur wherever the voltage is raised to the point that the device goes into avalanche.
MOSFET
140
, shown in
FIG. 3
, is variation of MOSFETs
100
and
130
, where the MOSFET cells
142
contain no deep P+region, and a diode cell
144
containing a deep P+region is distributed at predetermined intervals throughout the array to act as a voltage clamp and limit the strength of the electric fields in the MOSFET cells. In MOSFET
140
, the gate oxide layer is of uniform thickness.
FIGS. 4A-4G
illustrate various aspects of the breakdown phenomenon.
FIG. 4A
shows the electric field strength contours at breakdown in a trench-gated device
150
having a relatively thick gate oxide layer. Device
150
is in effect a gated diode, a structural element of most trench-gated vertical power MOSFETs. As indicated, the strongest electric field, where impact ionization would occur during avalanche breakdown, is located at the junction directly beneath the P+body region. In contrast, device
160
, shown in
FIG. 4B
, has a relatively thin gate oxide layer. While some ionization still occurs underneath the P+region, the highest electric field levels are now located near the corner of the trench. A field plate induced breakdown mechanism causes the strength of the electric field to increase.
FIGS. 4C and 4D
show the ionization contours of devices
150
and
160
, respectively, when they go into avalanche breakdown. Whether there is a thick ate oxide layer, as in
FIG. 4C
, or thin gate oxide layer, as in
FIG. 4D
, eventually in “deep” avalanche, i.e., when the device is forced to conduct largie currents in avalanche, breakdown starts to occur at the corner of the trench. Even in the thick oxide case (FIG.
4
C), where the peak electric field is not at the corner of the trench (FIG.
4
A), as the drain voltage increases eventually ionization occurs at the corner of the trench. However, there are more contours in
FIG. 4D
, indicating a higher ionization rate where the gate oxide layer is thin.
FIG. 4E
shows that if one introduces a diode clamp including a deep P+region, as shown on the right-hand side, the diode will break down at a lower voltage. and avalanche breakdown should not occur at the corner of the trench. If the resistance of the current path through the diode is low enough, then the diode will clamp the maximum voltage of the device. As a result, the voltage will never rise to the point that avalanche breakdown occurs near the corners of the trenches.
FIG. 4F
is a graph showing the breakdown voltage (BV) as a function of gate oxide thickness (X
OX
) for 20 V and 30 V devices. The doping concentration of the epitaxial (epi) layer in the 30 volt device is more lightly doped. The 30 V device would ideally have an avalanche breakdown of around 38 volts. In the 20 volt device the epi would be more heavily doped and the device would ideally have an avalanche breakdown of around 26 or 27 V. As the gate oxide is thinned from 1,000 Å to a few hundred Å, basically the breakdown voltages are relatively constant or may actually even increase somewhat as the shape of the field plate of the gate is actually beginning to help relax the electric field. At thicknesses of less a few hundred Å, however, breakdown degradation begins to occur.
Beyond the point where the breakdown voltage begins to drop (below 30 V for the 30 V device epi and below 20 V for the 20 V device) is the area labeled field plate induced (fpi) breakdown. In this area, breakdown occurs near the trench. For a reliable device one needs to add a diode clamp having a breakdown that is lower than the breakdown in the field plate induced area, so that the diode breaks down first. With a diode having a breakdown voltage as shown in
FIG. 4F
, breakdown would never occur near the gate in the 30 V device, but that diode would have too high a breakdown voltage to protect a 20 V device. To protect the 20 V device, the breakdown voltage of the diode clamp would have to be below the curve for the 20 V device.
FIG. 4G
is a schematic diagram of the devices shown in
FIGS. 4A-4D
showing a gated diode in parallel with a MOSFET and a diode voltage clamp in parallel with both the MOSIFET and gated diode. The arrangement is designed such that the diode clamp breaks down first. The gated diode never “avalanches” before the diode clamp. This becomes more and more difficult to do as the gate oxide layer becomes thinner.
FIGS. 5A and 5B
show the ionization contours in a device
170
having a sharp trench corner and a device
172
having a rounded trench corner.
FIG. 5B
indicates that rounding the trench corners does reduce the magnitude of the io

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