Process of fabricating semiconductor device having ashing step f

Details Process of fabricating semiconductor device having ashing step f Process of fabricating semiconductor device having ashing step f

1998-11-17

2000-09-26

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438708, 438725, 438743, H01H 100

Patent

active

061242136

ABSTRACT:
A photo-resist mask is removed from an inter-level insulating structure by using plasma produced from N.sub.x H.sub.y gas, and the plasma does not make an organic insulating layer forming part of the inter-level insulating structure hygroscopic, because SiCH.sub.3 bond is never replaced with Si--OH bond during the removal of the photo-resist mask.

REFERENCES:
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patent: 6010965 (2000-01-01), Shelds
patent: 6013576 (2000-01-01), Wang et al.
patent: 6019906 (2000-02-01), Jang et al.
Japanese Office Action dated Sep. 9, 1999, with partial translation.
Hasegawa, et. al., Process Technology for Devices, "Groping for Low Dielectric Constant Material Available for Inter-level Layer" "Low Dielectric Constant Achieved by Using Fluorine-Contained Resin Etching", Semiconductor World, Feb. 1997, pp. 82-84, with partial translation.
Furusawa, et. al., "Low Capacitance Multilevel Interconnection Using Low-E Organic Spin-on Glass for Qyuarter-Micron High-Speed ULSIs", 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 59-60.

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