Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-12-10
2000-10-17
Nelms, David
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438264, 438257, 438303, 438622, 438629, 438634, H01L 21336
Patent
active
061330965
ABSTRACT:
A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.
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Chen Jong
Kuo Di-Son
Lin Chrong-Jung
Su Hung-Der
Ackerman Stephen B.
Dang Phuc T.
Nelms David
Saile George O.
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