Static information storage and retrieval – Read/write circuit
Patent
1988-06-01
1990-08-14
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
365208, G11C 702
Patent
active
049493060
ABSTRACT:
A highly integrated memory features increased reading speed and writing speed. A sense circuit for this memory including a memory cell array having a plurality of memory cells each of which including at least one insulated gate field effect transistor, and a plurality of data lines to which the memory cells are connected. The memory also includes an address selection mechanism which is capable of selecting a memory cell out of a plurality of memory cells and connecting it to the data line. A sense amplifier a mechanism which is connected to the data line and amplifies a voltage according to the data of a memory cell. A common line (input/output line) is connected to the data lines, via a column switch, where the selection depends upon a column address. A main amplifier is connected to the common line (input/output line), and has at least a mechanism for stabilizing the voltage of the common line (input/output line) and an amplifying mechanism.
REFERENCES:
patent: 4150441 (1979-04-01), Ando
patent: 4479202 (1984-10-01), Uchida
patent: 4724344 (1988-02-01), Watanabe
"A 65 ns CMOS 1Mb Dram", Webb et al., IEEE International Solid-State Circuits Conference, 1986, pp. 262 and 263.
Aoki Masakazu
Horiguchi Masashi
Ikenaga Shin'ichi
Itoh Kiyoo
Nakagome Yoshinobu
Hitachi , Ltd.
Moffitt James W.
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