Process for reducing copper oxide during integrated circuit fabr

Details Process for reducing copper oxide during integrated circuit fabr Process for reducing copper oxide during integrated circuit fabr

1997-12-22

2000-03-07

Green, Anthony

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

438694, 438695, 438703, 438710, 438720, 438722, 438759, H01L 2100

Patent

active

06033584&

ABSTRACT:
A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.

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D.R. Evans, Y. Ono, J.F. Wang, A.R. Sethuraman, and L. M. Cook, Yield and Defect Characterization of Copper CMP Metallization, Aug. 13, 1999, pp. 1-4.
The Associated Press, IBM Unveils Copper-based Chip, Sep. 21, 1997, pp. 1-2.
Semiconductor Equipment: Source, Technical Showcase, Research Center Chooses MB.sup.2 for CVD Copper Interconnect, Winter 1997 (No Month).
Andrew Brooks, IBM Disclosure Fast Copper-Based Chip (Sep. 22), 1997, pp. 1-2.
Jiun-Fang Wang, Anantha R. Sethurarnan, Lee M. Cook, David R. Evans, and Victoria L. Shannon, Surface: Technology Review, Chemical Mechanical Polishing of Copper Metallized Multilevel Interconnect Devices, Fall 1994, pp. 1-4 (No Month).

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