Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-11-27
2007-11-27
Toledo, Fernando L. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S241000, C438S287000, C438S685000, C438S773000, C257SE21194, C257SE21582
Reexamination Certificate
active
11553690
ABSTRACT:
When an oxidation treatment for regenerating a gate insulating film6is performed after forming gate electrodes7A of a polymetal structure in which a WNxfilm and a W film are stacked on a polysilicon film, a wafer1is heated and cooled under conditions for reducing a W oxide27on the sidewall of each gate electrode7A. As a result, the amount of the W oxide27to be deposited on the surface of the wafer1is reduced.
REFERENCES:
patent: 4282270 (1981-08-01), Nozaki et al.
patent: 4505028 (1985-03-01), Kobayashi et al.
patent: 4914059 (1990-04-01), Nissim et al.
patent: 5088314 (1992-02-01), Takashi
patent: 5202096 (1993-04-01), Jain
patent: 5387540 (1995-02-01), Poon et al.
patent: 5693578 (1997-12-01), Nakanishi et al.
patent: 5719410 (1998-02-01), Suehiro et al.
patent: 6066508 (2000-05-01), Tanabe et al.
patent: 6162741 (2000-12-01), Akasaka et al.
patent: 6664196 (2003-12-01), Wada et al.
patent: 2001/0042344 (2001-11-01), Ohmi et al.
patent: WO97/28085 (1997-08-01), None
patent: WO98/39802 (1998-09-01), None
patent: 964437 (1999-12-01), None
patent: 56-107552 (1981-08-01), None
patent: 59-10271 (1984-01-01), None
patent: 60-72229 (1985-04-01), None
patent: 60-89943 (1985-05-01), None
patent: 60-107840 (1985-06-01), None
patent: 60-123060 (1985-07-01), None
patent: 61-127123 (1986-06-01), None
patent: 61-127124 (1986-06-01), None
patent: 61-150236 (1986-07-01), None
patent: 61-152076 (1986-07-01), None
patent: 61-267365 (1986-11-01), None
patent: 1-94657 (1989-04-01), None
patent: 3-119763 (1991-05-01), None
patent: 3-147328 (1991-06-01), None
patent: 5-141871 (1993-06-01), None
patent: 5-144804 (1993-06-01), None
patent: 5-152282 (1993-06-01), None
patent: 6-115903 (1994-04-01), None
patent: 6-120206 (1994-04-01), None
patent: 6-163871 (1994-06-01), None
patent: 6-333918 (1994-12-01), None
patent: 7-94716 (1995-04-01), None
patent: 7-94731 (1995-04-01), None
patent: 7-321102 (1995-12-01), None
patent: 8-83772 (1996-03-01), None
patent: 8-264531 (1996-10-01), None
patent: 9-75651 (1997-03-01), None
patent: 9-172011 (1997-06-01), None
patent: 9-298170 (1997-11-01), None
patent: 10-223900 (1998-08-01), None
patent: 10-335652 (1998-12-01), None
patent: 10-340909 (1998-12-01), None
patent: 11-26395 (1999-01-01), None
patent: 11-31666 (1999-02-01), None
patent: 11-204456 (1999-07-01), None
patent: 11-330468 (1999-11-01), None
patent: 2000-36593 (2000-02-01), None
patent: 2000-68502 (2000-03-01), None
patent: 2000-118491 (2000-04-01), None
patent: 2000-331978 (2000-11-01), None
patent: 2000-349285 (2000-12-01), None
Yasuo Tarui, “Handoutai Process Handbook,”Press Journal, Receiving date at Japan Patent Office: Mar. 30, 1999, pp. 153-157.
Kazuo Maeda, Saishin LSI Process Gijutsu, Kogyo Chosakai, Apr. 20, 1988, pp. 111-113.
Yasushi Akasaka et al., “Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperture Processing,”IEEE Transactions on Electron Devices, vol. 43, No. 11, Nov. 1996, pp. 1864-1869.
K. Nakajima et al., “Formation Mechanism of Ultrathin WSiN Barrier Layer in a W/WN×/Si System,”Applied Surface Science 117/118(1997), pp. 312-316.
K. Nakajima et al., “Poly-metal Gate Process-Ultrathin WSiN Barrier Layer Impermeable to Oxidant In-diffusion During Si Selective Oxidation,” Advanced Metallization Conference Japan Session, Tokyo University, 1995.
K. Nakamura et al., “Hydrogen-Radical-Balanced Steam Oxidation Technology for Ultra-Thin Oxide with High Reliability,”Proceedings of the 45thSymposium on Semiconductors and Integrated Circuits Technology, Tokyo, Japan, Dec. 1993, pp. 128-133.
E. Kneer et al., “Electrochemistry of Chemical Vapor Deposited Tungsten Films with Relevance to Chemical Mechanical Polishing,”J. Electrochem. Soc., vol. 143, No. 12, pp. 4095-4100.
Maeda, K.,Latest LSI Processing Technology, Kogyo Chosakai Publishing Co., 1983, pp. 111-113 (with English translation).
Yamada, M.,Handbook of Semiconductor Processing, Ch. 1, Section 17, pp. 153-157, Oct. 15, 1996 (with English translation).
Hozawa Kazuyuki
Kimura Shin'ichiro
Nishitani Eisuke
Suzuki Norio
Uchiyama Hiroyuki
Miles & Stockbridge PC
Renesas Technology Corp.
Toledo Fernando L.
LandOfFree
Process for producing semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for producing semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for producing semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3821749