Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-08
2001-08-07
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000
Reexamination Certificate
active
06271074
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated semiconductor circuit, such as an A/D converter, including a first zone in which capacitors are disposed, the capacitors having capacitor plates being formed of a first conductive layer and a second conductive layer, and a second zone in which circuit elements are disposed. The invention also relates to a process for producing the circuit.
In many types of integrated semiconductor circuits, the problem of producing one or more capacitors with a very precisely defined capacitance plays a major role. The absolute value of the capacitance and/or the relative accuracy of the capacitance of the different capacitors can be essential.
One example thereof are A/D converters, which are typically made with the aid of capacitor networks. For that purpose, in 8-bit converters, for instance, the capacitors must have a relative accuracy of less than 200 ppm. That is necessary, since for unequivocal conversion of analog signals to digital signals or vice versa, there must be a monotonic relationship between the analog signal and the digital signal, or at least the non-monotony must be less than one hit (namely the least significant bit or LSB). The matching behavior of the circuit is determined, among other factors, by how well that requirement is met (see IEEE Transactions on Circuits and Systems, Vol. 25, No. 7, July 1978, p. 419).
In CMOS processes, for instance, suitable capacitances can be achieved in different planes, such as polysilicon to substrate, polysilicon 1 to metal 1, polysilicon 1 to polysilicon 2, or metal 1 to metal 2. In the polysilicon planes as capacitor plates, it must be taken into account that the dopings must be relatively high (approximately 1020/cm
2
), if the necessary constancy is to be achieved upon a voltage change. Such high dopings cannot always meet the requirements of the overall process in terms of the gate polysilicon, or they necessitate an additional doping with a mask in the silicon substrate. If polysilicon and substrate are used for the capacitance, then because of the usually slight gate oxide thicknesses of modern CMOS generations, high specific capacitances are attained, which is deleterious to the recharging time. However, given sufficiently low structural tolerances of lithography and etching processes, adequately small capacitor surface areas (to increase the speed) can be produced with the necessary accuracy. At least in process options that have two polysilicon planes, it may be advantageous, in terms of those peripheral conditions, to produce the capacitances using one or both polysilicon planes.
If only one polysilicon plane is processed, then often a metal 1/metal 2 capacitance is more suitable. It is also successfully used in 0.7 &mgr;m CMOS generations, for 10-bit A/D converters with linearities of 0.5 LSB.
Particularly in future generations, the dielectric between the conductive layer, from which the capacitor plates are formed, must be planarized over a long range. For example, the typical planarizing lengths in the intermetal dielectric, when spin-on glass (SOG) planarizing techniques are employed, are from 10 to 100 &mgr;m. Given the typical dimensions of an A/D converter capacitor network of a few hundred micrometers, this leads to unacceptable fluctuations in the thickness of the capacitor dielectric. In 10-bit A/D converters, the planarizing with SOG already leads to errors in linearity of from 2 to 4 LSB, and therefore to massive yield losses because of the occurrence of what are known as missing codes.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor circuit with capacitors of precisely defined capacitance and a process for producing the circuit, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and processes of this general type and which improve an absolute or relative accuracy of the capacitance of one or more capacitors.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor circuit, comprising a first zone having capacitors disposed therein, the capacitors having capacitor plates being formed of a first conductive layer and a second conductive layer; a second zone having circuit elements disposed therein; a planarizing layer and a cover layer insulating the first and second conductive layers from one another in the second zone, except for a possible peripheral region; and a dielectric being formed only of the cover layer between the capacitor plates in the first zone, except for a possible peripheral region.
In accordance with another feature of the invention, the cover layer is formed of silicon oxide.
In accordance with a further feature of the invention, the conductive layers are formed of polysilicon, and the planarizing layer is formed of silicon oxide.
In accordance with an added feature of the invention, the first conductive layer is formed of polysilicon, the second conductive layer is formed of a material selected from the group consisting of metal and a metal alloy, and the planarizing layer is formed of a doped silicate glass.
In accordance with an additional feature of the invention, the conductive layers are formed of a material selected from the group consisting of metal and a metal alloy, and the planarizing layer is formed of silicon oxide and an auxiliary layer.
In accordance with yet another feature of the invention, the capacitors have a capacitance being adjusted by the thickness of the cover layer.
With the objects of the invention in view, there is also provided an A/D converter which is constructed according to the foregoing.
With the objects of the invention in view, there is additionally provided a process for producing an integrated semiconductor circuit including a first zone, capacitors being disposed in the first zone and having capacitor plates formed of a first conductive layer and a second conductive layer, a second zone, and circuit elements disposed in the second zone, which comprises producing the first conductive layer; applying an insulating planarizing layer after producing the first conductive layer; removing the planarizing layer in the first zone until a surface of the first conductive layer is exposed, except for a possible peripheral region; applying an insulating cover layer over the entire surface; and producing the second conductive layer.
In accordance with another mode of the invention, there is provided a production process which comprises carrying out the step of removing the planarizing layer with the aid of a photographic technique using a photomask having a separate window for each respective capacitor of the first zone.
In accordance with a concomitant mode of the invention, there is provided a production process which comprises carrying out the step of removing the planarizing layer with the aid of a photographic technique using a photomask having one continuous window for all of the capacitors of the first zone.
In the invention, the insulating layer between the two conductive layers includes a planarizing layer and a cover layer in the second zone, in which only circuit elements in which the requirement for accuracy of the capacitance is low are disposed in the second zone. In the first zone, in which one or more capacitors with a capacitance that must be adjusted precisely are disposed, the insulating layer between the capacitor plates includes only the cover layer.
In order to produce such a configuration, processes may be considered, in particular, in which in the first zone the planarizing layer above the first conductive layer is removed again entirely, optionally except for a peripheral region of the first zone, which depends upon the accuracy of adjustment. The thickness of the capacitor dielectric formed of the cover layer is accordingly very uniform and can be adjusted precisely. The matching behavior is decisively improved thereby, and if the construction rules change (such as a change in the capacitor s
Fischer Elisabeth
Hain Manfred
Chaudhuri Olik
Greenberg Laurence A.
Lerner Herbert L.
Pham Hoai
Siemens Aktiengesellschaft
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