Process for planarizing array top oxide in vertical MOSFET...

Details Process for planarizing array top oxide in vertical MOSFET... Process for planarizing array top oxide in vertical MOSFET...

2005-05-24

2005-05-24

Kennedy, Jennifer M. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S386000, C438S387000

Reexamination Certificate

active

06897108

ABSTRACT:
The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.

REFERENCES:
patent: 6261894 (2001-07-01), Mandelman et al.
patent: 6509226 (2003-01-01), Jaiprakash et al.
patent: 6548344 (2003-04-01), Beintner et al.
patent: 6620676 (2003-09-01), Malik et al.
patent: 6727540 (2004-04-01), Divakaruni et al.
patent: 6790739 (2004-09-01), Malik et al.
patent: 6821843 (2004-11-01), Chen et al.
patent: 20010023957 (2001-09-01), Warwick
patent: 63252467 (1988-10-01), None
patent: 02081472 (1990-03-01), None

Affiliated with

Also associated with

Rating

Process for planarizing array top oxide in vertical MOSFET... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for planarizing array top oxide in vertical MOSFET..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for planarizing array top oxide in vertical MOSFET... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3444330