Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-25
2001-10-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000
Reexamination Certificate
active
06300195
ABSTRACT:
TECHNICAL FIELD
This invention relates to an improved process for manufacturing semiconductor integrated electronic memory devices with a cell matrix having a virtual ground, and more specifically, to manufacturing memory devices made from floating gate memory cells and having a plurality of continuous bit lines extending across a substrate as discrete parallel strips.
BACKGROUND OF THE INVENTION
The invention relates, particularly but not exclusively, to a process for manufacturing electronic semiconductor integrated electronic memory with cells matrix having virtual ground, and throughout the following description, reference will be made to that technical field for convenience of illustration. Discussion of elements or fabrication processes well known to those skilled in the art has been abbreviated or eliminated for brevity.
Electronic semiconductor-integrated EPROM or Flash EPROM memory devices include a plurality of non-volatile memory cells organized in matrix form; that is, the cells are arranged therein into rows, or word lines, and columns, or bit lines.
Each non-volatile memory cell includes a MOS transistor having a floating gate electrode located above the channel region. The floating gate electrode has a high D.C. impedance to all the other terminals of the same cell and the circuit whereto the cell is incorporated.
Each cell also has a second electrode, or control gate, which is driven by means of appropriate control voltages. The other transistor electrodes are, as usual, the drain and source terminals.
In recent years, considerable effort went to the development of memory devices with increased circuit density. This effort resulted in electrically programmable non-volatile memory matrices of the contactless type being developed which have a so-called “tablecloth” or crosspoint structure. An example of matrices of this kind, and their manufacturing process, is described in European Patent No. 0 573 728 of this applicant, incorporated herein by reference.
In matrices of this type, the matrix bit lines are formed in the substrate as continuous parallel diffusion strips. These matrices are formed by memory cells which comprise floating gate capacitive coupling MOS devices.
The process flow for manufacturing such memory cells includes forming, on a semiconductor substrate, mutually parallel stack strips which have a first layer of gate oxide, a layer of first polysilicon, an interpoly oxide layer, and a layer of second polysilicon.
An implantation step is then carried out to form the bit lines, and after the deposition of a planarizing layer, the matrix word lines are formed.
In the prior art, the gate regions of the individual cells are then defined by self-aligned etching. However, this first solution has several drawbacks, one of which is that in cells having small size, the self-aligned etch step becomes more critical.
SUMMARY OF THE INVENTION
An embodiment of the invention provides a process for defining memory cells, arranged into matrices of the crosspoint type, which have such structural and functional features as to avoid the need for a critical gate region defining step, thereby overcoming the limitations and drawbacks which still beset the memory cells of prior art crosspoint matrices. One embodiment of the invention fully defines each gate region of the matrix cells by means of an oxide island, before the matrix bit lines are defined.
In one embodiment of the invention, a process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and comprising at least a matrix of floating gate memory cells is provided. The matrix is formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips. The method includes first forming an oxide layer over the matrix region, and depositing on the semiconductor a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Then a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY
1
along a first direction”, and associated etching is used to form, in the stack structure, a plurality of parallel openings. Next the parallel openings are implanted to confer a predetermined conductivity on the bit line regions. Finally, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.
The features and advantages of a device according to the invention will become apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5087584 (1992-02-01), Wada et al.
patent: 5346586 (1994-09-01), Keller
patent: 5723350 (1998-03-01), Fontana et al.
patent: 6057192 (2000-05-01), Colabella
patent: 0 573 728 A (1993-12-01), None
patent: 55 08323 A (1980-06-01), None
patent: 60 059737 A (1985-04-01), None
patent: WO 94/20989 (1994-09-01), None
Brambilla Claudio
Caprara Paolo
Cereda Sergio
Irani Rustom
Pozzoni Pierantonio
Galanthay Theodore E.
Iannucci Robert
Nelms David
Nhu David
Seed IP Law Group PLLC
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