Process for manufacturing semiconductor devices having raised do

Details Process for manufacturing semiconductor devices having raised do Process for manufacturing semiconductor devices having raised do

1998-03-24

1999-12-14

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438300, 438301, 438672, 438692, 438564, H01L 21336

Patent

active

060016973

ABSTRACT:
A method of manufacturing a raised source/drain semiconductor device is disclosed. When the shallow junction technique is applied, over etching of the source/drain regions during contact etching and salicide processing will lead to current leakage. The invention provides a method which comprises depositing a buffer conductive layer above the substrate and removing a portion of this layer to form buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions.

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Wakabayashi et al, "A high-performance 0.1 micron CMOS with elevated salicide using novel SiOSEG process," IEDM IEEE 5.1.1-5.1.4, 1997.
Mirabedini et al, "Submicrometre elevated source and drain MOSFET technology using E-beam evaporated silicon," Electronic Letters vol. 33, No. 13, Jun. 19, 1997.

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