Process for making low dielectric constant hollow chip...

Details Process for making low dielectric constant hollow chip... Process for making low dielectric constant hollow chip...

2000-07-19

2003-07-22

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S633000

Reexamination Certificate

active

06596624

ABSTRACT:

DESCRIPTION
1. Field of the Invention
This invention relates to high density microminiaturized electronic circuit devices. More particularly, this invention relates to multilevel structures, and the formation of multilevel structures, comprised of alternating via levels and wiring levels embedded in a low dielectric constant medium and mounted on chip carriers.
2. Background of the Invention
Electrically integrated structures having multiple levels of conductive wiring horizontally supported in or on a dielectric material and vertically separated by intermediate levels of dielectric material are well known. Typically, alternating levels of wiring and vias can be quite numerous and complex in layout. The continuing drive toward reduction in dimensions and increase in density of features within these structures is inspired by aggressive requirements of memory, logic and storage density. Smaller device structures result in higher bit density, lower operating voltage, lower energy consumption and faster device speed. Smaller device structures require proportionately narrower and shorter conductor lines, narrower diameter vias and lower dielectric constant materials.
Increased also are the problems associated with such miniaturization and the proximity of the features to one another, including the risks of shorting, crosstalk and capacitive coupling between and especially within wiring levels, additional heat generation due to IR drop and the risk of failure due to electromigration and impeded signal speed.
As the design of the multilevel circuit structures becomes more aggressive, the need to reduce the dielectric constant (Er) of the dielectric insulating material to a value closer to the ideal value of value 1.0 in air or vacuum becomes a necessity. The lower the Er, the faster the signal speed and the rise time and the less the capacitive interaction. Lower Er permits operation of the device at a lower voltage which will result in lower thermal heating due to IR drop. In highly compact IC structures, the Er must be lowered not only in the via interlevels between wiring levels, but more importantly intralevel—within each wiring level. It is more critical to obtain extremely densely patterned circuitry levels separated by extremely low Er dielectric material between adjacent conductor lines within each wiring level to avoid capacitative interaction within the dense wiring levels. The lower the Er, the closer to each other can the lines in a wiring level be placed. It is therefore in the wiring level that the dielectric medium is more beneficially air, another suitable gas, or vacuum, i.e. a hollow structure.
Heat conductors in via levels and horizontal air movement through a hollow structure assure the elimination of any “hot spots”. Hot spots would contribute greatly to stress induced electromigration. Likewise, removing the additional heat generated by the densely configured operating structure and maintaining a low weight contribution to the ultimate device, for example such as laptop and hand-held devices, are important problems to solve in building high performance structures of the future.
Various materials, such as polyimide, epoxies, FR4-type resins, cyclotene, polymethyl methacrylate (PMMA) and Novolac-type resins, as well as fluorocarbons and others have been used as dielectric material in multilevel packaging structures, often with additives and fillers to affect properties such as thermal expansion (to reduce cracking and dislocation resulting from differing coefficients of thermal expansion among materials used in the structure), flame retardance, and Er. A high performance dielectric material might have an Er of about 3.2 to about 5.0; a pure fluoropolymer might have an Er as low as 2.1, a polyimide about 3.1 to about 3.5. In order to reduce further the Er to a number more nearly approaching the ideal value of pure air, various materials such as foam or hollow microspheres have been added to the resinous dielectric, the latter as described in U.S. Pat. No. 5,126,192 issued Jun. 30, 1992 to Chellis et al. and assigned to the assignee of the present invention. As the dimensions of the circuitry and particularly the spaces between the individual conductor lines on any one level continue to decrease it is becoming more and more difficult to introduce hollow microspheres or foam dielectrics because the walls of the microspheres or the walls between air bubbles in the foam approach the dimension of the spaces between the conductor lines which is 1500A, 1000A, and eventually 500A.
Until recently in integrated circuit manufacturing, plated wiring was embedded in a dielectric material such as SiO2, polyimide, a combination of SiO2 and Si3O4, or other. One of the newer dielectric products is SiLK, a trademark product of Dow Chemical Company, which is a partially polymerized oligomeric spin-on material in a high purity NMP carrier solvent. The dielectric material provides electrical separation between and physical support for the individual conductor lines in the wiring levels. Support is particularly important in those structures which are built using a damascene process. Silicon dioxide has an Er of about 3.9 to about 4.5 and polyimide about 3.5, leaving room for improvement in current commercial structures as well as demanding improvement for structures of the future.
An article on pp. 575-585 published in the IBM Journal of Research and Development Volume 42 No. 5, September 1998, “Electrochemical process for advanced package fabrication”, coauthored by S. Krongelb, J. A. Tornello and L. T. Romankiw, the latter of whom is the inventor herein, includes a description of a process of making, and certain performance measurements of, a multilevel structure which incorporates polyimide dielectric layers and is on a chip carrier. In preparation for creating the scanning electron micrograph (SEM) images of the structure, seen as FIGS. 3 and 4 on p. 580 and FIG. 5 on p. 581, polyimide was removed from a region of the structure by ashing in an oxygen containing plasma. Electrical measurements were performed in order to ascertain that the metallurgy was sound and that good metal-to-metal contact had been obtained during electroplating. The present invention, in which solid dielectric material is replaced by air or vacuum in order to obtain a mechanically sound, multilevel final structure having minimal Er, was not foretold by the reference. Up to the time of the present invention it was assumed that dielectric such as polyimide would provide an minimum Er which would be adequate for the thin film package (chip carrier).
An article on pp. 49-51 published in the journal Electrochemical and Solid State Letters published by the Electrochemical Society, Inc., 1(1), 1998, “Air-Gaps for electrical Interconnections” is coauthored by Paul L. Kohl, Qiang Zhao, Kaushal Patel, Douglas Schmidt, Sue Ann Bidstrup-Allen, Robert Shick and S. Jayaraman. The reference describes the thermal decomposition of a sacrificial polymer at a temperature ramped up to 425 then to 450 degrees C. The sacrificial polymer is removed from between two metal line levels which are fully encapsulated within a permanent dielectric overcoat, and the products of the heat decomposition of the sacrificial polymer, less a thin residue, are forced out by diffusing through the overcoat, leaving a gap remaining in the region occupied by the polymer prior to its decomposition. It is stated in the reference that the effective dielectric constant between the two levels can be lowered to 2.3-2.7 for structures with a 1:1 aspect ratio (h:w), or perhaps lower, depending on the thickness and dielectric constant of the permanent overcoat. Clearly, the technique of thermal decomposition is quite different from that of the present invention. The feasibility of adapting and implementing a thermal decomposition technique in a manufacturing environment would be highly problematic. In order to manufacture a workable device it would be necessary to be able to fabricate more than two conductor line levels. That is would be possible to do so and

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