Process for making a DRAM cell with three-sided gate transfer

Details Process for making a DRAM cell with three-sided gate transfer Process for making a DRAM cell with three-sided gate transfer

2000-05-05

2001-11-27

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S249000, C438S296000, C438S129000, C438S947000

Reexamination Certificate

active

06323082

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to a semiconductor device and a process of manufacturing a semiconductor device. More specifically, this invention relates to a dynamic random access memory (DRAM) semiconductor device having a three-sided-gate transfer device and a process for manufacturing the same.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is an incentive to reduce the size of each semiconductor device on a chip. A smaller device can allow an increased density of devices on a chip and can help semiconductor manufacturers reduce cost and improve performance of a chip. When the size of a DRAM device or cell is reduced, more DRAM cells can fit on a chip of a certain size, resulting in increased memory storage capability of the chip.
The size of a DRAM device may be reduced by designing the DRAM device or cell in three-dimensions. This may reduce the semiconductor surface area used by each DRAM cell. For example, using trench capacitors in a DRAM cell may result in a reduced semiconductor surface area used by the DRAM cell.
FIG. 1
shows a cross section of a buried plate trench DRAM cell
100
as described by Donald M. Kenney in U.S. Pat. No. 5,348,905.
The DRAM cell
100
in
FIG. 1
is formed in a p-type semiconductor substrate
10
. A p-type well
12
is formed in the upper surface of the substrate
10
. An n-channel transfer device
14
is formed within the p-type well
12
. The transfer device
14
couples data between a bit-line (not shown) that is connected to the bit-line diffused n-type region
18
and the diffused n-type storage node region
20
. The gate electrode
16
is connected to a word line (not shown) and controls the transfer of data through the channel
34
of the transfer device
14
.
A storage capacitor is formed in a deep trench
22
adjacent diffused n-type storage node region
20
. The storage capacitor includes a signal storage node
24
in the deep trench
22
which is isolated from substrate
10
by a thin dielectric layer (not shown). The diffused n-type storage node region
20
and the signal storage node
24
in the deep trench
22
are connected by a conductive strap
26
. An insulating collar
28
decreases leakage of stored charge between diffused n-type storage node region
20
and buried n-type layer
32
. The surface region of substrate
10
occupied by the DRAM cell
100
is defined by local surface isolation
30
.
The buried n-type layer
32
acts as the reference voltage node for the trench capacitor and forms electrical and physical isolation between the p-type well
12
and the substrate
10
. As known to those skilled in the art, reference voltages V
bn
, V
bp
, and V
sub
may be used to bias the device
100
.
FIGS. 2A-2D
illustrate a three-sided gated DRAM cell in a diagonal bit-line configuration. K. Shibahara et al.,
1
GDRAM Cell With Diagonal Bit-Line (DBT) Configuration and Edge Operation MOS(EOS) FET
, IEDM Technical Digest, 639-42 (1994). As shown in
FIGS. 2A and 2B
, the device
200
is formed in a substrate
202
. The device
200
has a channel
206
coated with a gate oxide
208
and a gate conductor
204
. The storage node of the device
200
is a stacked capacitor. Id. at
640
.
FIG. 2B
shows the device
200
in operation where an inversion layer
210
is formed at a corner
212
of the channel
206
.
FIG. 2C
shows the layout of a device
200
, defined by a boundary
216
, that occupies a 6F
2
(3F×2F) size area of the substrate
202
, where F is the minimum lithographic dimension. As shown in
FIG. 2C
, the device
200
does not have any sub-lithographic dimensions.
Recessed LOCOS (local isolation of silicon) isolation regions are used to isolate the device
200
rather than using shallow trench isolation (STI) regions. Id. at
640
(see first paragraph). As shown in
FIG. 2D
, the LOCOS isolation regions form a birds beak
214
which may result in enough mechanical stress to cause dislocations of the silicon lattice and cause silicon defects.
FIG. 3
illustrates a MOSFET (metal oxide semiconductor field effect transistor) device
300
gated on three sides. K. Hieda et al.,
Effects of a New Trench
-
Isolated Transistor Using Sidewall Gates
, IEEE Transactions on Electron Devices, Vol. 36(9), 1615-19 (1989). The device
300
formed in a substrate
302
includes a drain
304
, a source
306
, and a three-sided gate
308
. Isolation regions
310
are formed on both sides of the device
300
. Each isolation region
310
is formed in a trench coated with an oxide layer
312
and then filled with polysilicon
314
.
By using a three-sided gate
308
, sidewall conduction of the channel
316
may be achieved. K. Hieda et al. teach that the above MOSFET device
300
is compatible with isolation merged DRAM and folded capacitor cells (see page 1616, column 2, first full paragraph) also known as stacked-in-trench cells. The device
300
is formed without a channel tailor implant on the sidewalls of the channel
316
(see page 1616, column 1, last paragraph).
To overcome the shortcomings of conventional DRAM devices, a new DRAM device is provided. An object of the present invention is to provide an improved DRAM device that has a reduced leakage current. A related object is to provide a process of manufacturing such a DRAM device. Another object is to provide a DRAM device that occupies a reduced semiconductor area. Another object is to provide a DRAM device having a sub-lithographic channel width on a substantially planar substrate surface. It is still another object to provide a DRAM device having a transfer device with a channel controlled from three sides. Yet another object is to provide a DRAM device having improved charge characteristics.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a DRAM device having reduced leakage current and a process of manufacturing the DRAM device. The DRAM device includes a signal storage node. A transfer device couples a bit-line contact to the signal storage node. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to the bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The mesa structure is controlled by a gate which is formed upon the first side, the second side, and the top of the mesa structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


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G. Bronner et al., A Fully Planarized 0.25m CMOS Technology for 256Mbit DRAM and Beyond, 1995 Symposium on VLSI Technology Digest of Technical Papers, 15-16 (1995).
L. Nesbit et al., A 0.6m2256 Mb Trench DRAM C

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