Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2008-07-01
2008-07-01
Lebentritt, Michael S. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S514000, C438S561000, C257SE21433, C257SE21585, C257SE21619
Reexamination Certificate
active
11119951
ABSTRACT:
A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.
REFERENCES:
patent: 5491099 (1996-02-01), Hsu
patent: 5858843 (1999-01-01), Doyle et al.
patent: 5880499 (1999-03-01), Oyama
patent: 5970329 (1999-10-01), Cha
patent: 5972762 (1999-10-01), Wu
patent: 6180465 (2001-01-01), Gardner et al.
patent: 6204137 (2001-03-01), Teo et al.
patent: 6214670 (2001-04-01), Shih et al.
patent: 6232188 (2001-05-01), Murtaza et al.
patent: 6440808 (2002-08-01), Boyd et al.
patent: 6479403 (2002-11-01), Tsei et al.
patent: 6495402 (2002-12-01), Yu et al.
patent: 6656764 (2003-12-01), Wang et al.
patent: 2002/0031891 (2002-03-01), Kim
patent: 2002/0187644 (2002-12-01), Baum et al.
patent: 2003/0124871 (2003-07-01), Arghavani et al.
patent: 2004/0087075 (2004-05-01), Wang et al.
Chen Chien-Hao
Chen Shih-Chang
Wang Ming-Fang
Yao Liang-Gi
Haynes & Boone LLP
Lebentritt Michael S.
Lee Cheung
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Process for integration of a high dielectric constant gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for integration of a high dielectric constant gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for integration of a high dielectric constant gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3953960