Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-12-23
2001-02-06
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06184073
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to semiconductor devices, and more particularly, to semiconductor devices having memory arrays with memory cells and processes for forming them.
BACKGROUND OF THE INVENTION
As device dimensions continue to shrink and the need to interconnect components within a semiconductor device increase, a need exists for advanced interconnecting systems that are robust and can be used for a variety of components in a semiconductor device. In many instances, these local interconnects may be made between a gate electrode and a source/drain region within a semiconductor substrate. When making this connection, difficulty can occur when etching an opening to extend through a thick insulating layer down to the gate electrode and the source/drain region. The gate electrode is etched for a longer time compared to the source/drain region because the gate electrode typically lies at a higher elevation than the source/drain region.
Some attempts to solve this problem include using etch-stop films. More specifically, a plasma enhanced nitride film can be formed over a gate electrode and a doped region within a substrate. A very thick oxide film is formed and planarized. The plasma enhanced nitride film over the gate electrode may be completely etched away before all the thick oxide film is etched over the source/drain region. This can occur because the etch selectivity between thick oxide film and plasma enhanced nitride is poor (typically less than 8:1).
Increasing the plasma enhanced nitride film thickness is not a good option because etch-stop films are typically less than 1000 angstroms thick, and the increased nitride thickness may make subsequent patterning of the etch-stop film more difficult. Increasing the thickness of the plasma enhanced silicon nitride film will increase the amount of nonuniformity in the remaining film thickness after the thick oxide film etch. Further, etch steps intended for removal of the plasma enhanced silicon nitride film will propagate the nonuniformity which is expected to cause loss of isolation at the most severely etched weak spots while still not clearing the film over source/drain regions. Also, the increased thickness of the plasma enhanced nitride film increases capacitive coupling to other conductors on the device.
In yet another attempt to solve the problem, a thin oxide film may underlie a nitride etch-stop film that is covered by the thick oxide film. Again, when etching through the thick oxide film, the nitride etch-stop film can be etched during the thick oxide film patterning. After the nitride etch-stop film is etched, the oxide etchants quickly remove the thin oxide film.
In still another attempt, a nitride film, an etch-stop polysilicon film, and a phosphorous glass film are sequentially formed. An opening is formed through the phosphorus glass film the etch-stop polysilicon film as an etch-stop film. The structure is subjected to a high pressure steam oxidation is performed and converts the etch-stop polysilicon to a thermal oxide film. An etch step is performed to extend the opening through the thermal oxide and nitride films. The high-pressure steam oxidation may cause undesired oxidation of other features present, such as gate electrodes.
A semiconductor device with a static random access memory (SRAM) memory cells are particularly prone to such contact problems when forming the cross-coupling between the storage nodes and the latch transistors. Referring to
FIG. 1
, SRAM cell
10
includes a pair of pass transistors
11
and
12
that are connected to a bit line (BL) and a complementary bit line ({overscore (BL)}), respectively. The other portion of transistor
11
is connected to the drains of the n-type latch transistor
13
and the p-type load transistor
15
. The other portion of the pass transistor
12
is connected to the drains of n-channel latch transistor
14
and p-channel load transistor
16
. As seen in
FIG. 1
, the gate electrodes of the latch transistor
13
and load transistor
15
are connected to the drains of transistors
14
and
16
. Also, the gate electrodes of transistors
14
and
16
are connected to the drains of transistors
13
and
15
. The sources of transistors
13
and
14
are connected to a V
SS
electrode, and the sources of the transistors
15
and
16
are connected to a V
DD
electrode. The gate electrodes for pass transistors
11
and
12
are part of a word line and are electrically connected to each other. In this particular SRAM cell
10
, difficulty is typically encountered when trying to cross-couple the inverters within the SRAM cell.
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Bhat Mousumi
Filipiak Stanley M.
Frisa Larry E.
Gelatos Carol M.
Lage Craig S.
Bowers Charles
Meyer George R.
Motorola Inc.
Thompson Craig
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