Process for fabrication of nitride layer with reduced...

Details Process for fabrication of nitride layer with reduced... Process for fabrication of nitride layer with reduced...

2005-10-18

2005-10-18

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S786000

Reexamination Certificate

active

06955965

ABSTRACT:
Process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate; forming on the semiconductor substrate a bottom oxide layer; depositing on the bottom oxide layer a nitride layer, the deposited nitride layer having a first hydrogen content; and applying a treatment to reduce the first hydrogen content to a second hydrogen content.

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U.S. Appl. No. 10/731,494, filed Dec, 9, 2003, entitled “Improved Process for Fabrication of Spacer Layer with Reduced Hydrogen Content in Semiconductor Device.”

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