Process for fabricating MOS memory devices, with a self-aligned

Details Process for fabricating MOS memory devices, with a self-aligned Process for fabricating MOS memory devices, with a self-aligned

1997-04-21

1998-08-11

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438666, 438649, H01L 218242, H01L 21336

Patent

active

057926840

ABSTRACT:
A semiconductor fabrication process has been developed in which both MOS memory devices and MOS logic devices are integrated on a single silicon chip. The process features combining process steps for both device types, however using a self-aligned contact structure, in the MOS memory device region, for purposes of increasing device density, while using metal silicide regions, only in MOS logic device regions, for purposes of improving device performance.

REFERENCES:
patent: 5066602 (1991-11-01), Takemoto et al.
patent: 5340762 (1994-08-01), Vora
patent: 5483104 (1996-01-01), Godinho et al.
patent: 5547893 (1996-08-01), Sung
patent: 5633181 (1997-05-01), Hayashi
patent: 5668035 (1997-09-01), Fang et al.

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