Process for fabricating MOS device having short channel

Details Process for fabricating MOS device having short channel Process for fabricating MOS device having short channel

1996-11-21

1999-07-20

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, 438305, H01L 21336

Patent

active

059267127

ABSTRACT:
The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration. The present invention is characterized in that no threshold voltage adjustment implantation to the semiconductor substrate is needed prior to the growth of the gate structure, and in stead, the diffusion ability of the pocket-implanted impurities in the step (c) can concurrently adjust the threshold voltage of the device.

REFERENCES:
patent: 4397887 (1983-08-01), Aytac et al.
patent: 5158903 (1992-10-01), Hori et al.
patent: 5449937 (1995-09-01), Arimura et al.
patent: 5466957 (1995-11-01), Yuki et al.
patent: 5518941 (1996-05-01), Lin et al.

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