Process for fabricating an integrated circuit with a self-aligne

Details Process for fabricating an integrated circuit with a self-aligne Process for fabricating an integrated circuit with a self-aligne

1998-03-27

1999-05-25

Quach, T. N.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438622, 438629, 438634, 438656, H01L 21335

Patent

active

059077816

ABSTRACT:
A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

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Ishigaki, Y., et al., Low Parasitic Resistance Technologies with NES-SAC and SWT-CVD Process . . . , 1994 IEEE Symposium on VLSI Technology Digest of Technical Papers, Jun. 7-9, 1994, pp. 99-100.
Kuesters, K., et al., "Self-Aligned Bitline Contact for 4 Mbit DRAM", Proceedings of the 1987 Symposium on ULSI Science and Technology, pp. 640-, 1984.

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