Process for fabricating a semiconductor structure having a self-

Details Process for fabricating a semiconductor structure having a self- Process for fabricating a semiconductor structure having a self-

1999-01-06

2000-07-18

Smith, Matthew

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

438705, 438640, 438249, 438568, H01L 21469

Patent

active

060907223

ABSTRACT:
A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.

REFERENCES:
patent: 4575921 (1986-03-01), Bhagat
patent: 5324990 (1994-06-01), Cunningham
patent: 5492793 (1996-02-01), Breyta et al.
patent: 5554485 (1996-09-01), Dichiara et al.
patent: 5585220 (1996-12-01), Breyta et al.
patent: 5626716 (1997-05-01), Bosch et al.
patent: 5915198 (1999-06-01), Ko et al.
patent: 5926730 (1999-07-01), Hu et al.
patent: 5937301 (1999-08-01), Gardner et al.
patent: 5948701 (1999-09-01), Chooi et al.
patent: 5960302 (1999-09-01), Ma et al.

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