Process for depositing layers on a semiconductor wafer

Details Process for depositing layers on a semiconductor wafer Process for depositing layers on a semiconductor wafer

2001-04-04

2003-03-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S250000, C438S393000

Reexamination Certificate

active

06534360

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process used in manufacturing a semiconductor device, and more particularly to a process used in manufacturing a stacked capacity element.
BACKGROUND OF THE INVENTION
The desire for greater capacity integrated circuits (ICs) on smaller sized devices has increased interest in replacing today's 64 megabit DRAM with memory devices in the range of 256 megabit, 1 gigabit and higher. This need for increased capacity in the same or smaller substrate footprint device makes it necessary to replace conventional dielectric films previously used in stacked capacitor formation, such as silicon dioxide (SiO
2
), with dielectric films having higher dielectric films having higher dielectric constants. Several factors significantly limit the potential capacitance of a polysilicon/oxide/polysilicon capacitor formation. The deposition of the oxide layer invariably causes some oxidation of the polysilicon layer thereby decreasing its functionality as a conductor. The dielectric constant “k” for SiO
2
is about 4. The dielectric constant of SiN is about 7. Thus, if a SiN electrode is used in this type of formation, and the polysilicon layer becomes oxidized, thereby interfacing with the SiN layer, the effective dielectric constant of the SiN layer is compromised, resulting in an effective “k” value of somewhere between 4 and 7, thereby degrading the performance of the capacitor.
Additionally, for front end formation of capacitors, the polysilicon layer will often contact the silicon substrate and this results in a phenomenon known as “parasitic capacitance”, which further degrades the potential capacitance of the polysilicon/oxide/polysilicon formation. Oxygen diffusion can be yet another concern for these types of structures.
Capacitors containing high-dielectric constant materials, such as Ta
2
O
5
, usually have much larger capacitance densities than standard SiO
2
-Si
3
N
4
-SiO
2
stack capacitors making them the materials of choice in IC fabrication. High dielectric constant films are desirable because they provide higher capacitance which enables closer spacing of devices without electrical interference which can increase transistor density. One material of increasing interest for stack capacitor fabrication is Tantalum Oxide which has a relative dielectric constant more than six times that of SiO
2
.
Deposition processes are employed to deposit thin films of insulative materials, as well as conductive, dielectric, ferroelectric and various other layers onto wafers. Such deposition has been performed through various well known processes, such as chemical vapor deposition (“CVD”) and physical vapor deposition (“PVD” or “sputtering”).
In a CVD process, a wafer is loaded into a chemical vapor deposition chamber. Conventional CVD processes supply reactive gases to the wafer surface where heatinduced chemical reactions take place to form a thin film layer over the surface of the wafer being processed. One particular CVD application is the deposition of a tantalum containing compound, such as tantalum oxide and tantalum nitride, which have dielectric constants on the order of 25 to 30. These compounds are deposited over a wafer from a process gas that includes a metallo-organic compound.
A carrier gas, such as helium, argon, nitrogen, or hydrogen brings the compound into the chamber, so that it may be infused with energy. The energy may be generated through a thermal heat source, in the case of thermal CVD, or a radio frequency (“rf”) signal source, in the case of plasma enhanced CVD. The energized chemical vapor reacts with the wafer's surface to form a thin layer of material on the wafer.
In a sputtering process, a wafer is placed in a physical vapor deposition (“PVD”) chamber, and the chamber is filled with a gas, such as argon. A plasma containing positively charged ions is generated from the gas, by creating an electrical field in the chamber. The positively charged ions accelerate and collide into a target material, which is mounted in the chamber. Atoms of the target material are thereby separated from the target and deposited on the wafer to form a layer of target material on the surface of the wafer.
In a traditional sputtering process, the bombardment of the target material by the positively charged ions is enhanced by providing a negative bias to the target material. This is achieved by providing a radio frequency signal to an electrode that supports the target material.
A separate RF signal may be inductively coupled to the chamber for generating positively charged ions in a high density plasma PVD chamber. A high density plasma PVD chamber may include another rf signal coupled to a wafer support for improving the attraction of the target material to the wafer.
A deposition chamber, such as a CVD chamber or a PVD chamber, may be used to deposit diffusion barriers in an integrated circuit. Diffusion barriers inhibit the diffusion of a contact metal, such as aluminum and copper, into the active region of a semiconductor device that is built on a silicon substrate. This prevents the interdiffusion of a contact metal into the substrate. Unlike an insulative layer of material, a diffusion barrier forms a conductive path through which current may flow. For example, a diffusion barrier may be employed to overlie a silicon substrate at the base of a contact hole.
A severe interdiffusion between a contact metal and a silicon substrate can begin to take place when the integrated circuit is heated to temperatures in excess of 450° C. If an interdiffusion is allowed to occur, the contact metal penetrates into the silicon substrate. This causes an open contact in the integrated circuit and renders the integrated circuit defective.
In the fabrication of integrated circuits, there has been an increased use of aluminum and copper metallization processes operating at high temperatures, in excess of 450° C. Therefore, it desirable to have diffusion barriers with a greater ability to inhibit the diffusion of contact metals, such as aluminum and copper.
In manufacturing an integrated circuit, it is desirable to perform successive steps of the manufacturing process in the same chamber (“in situ”). In situ operations reduce the amount of contamination that a wafer is exposed to by decreasing the number of times that the wafer is required to be transferred between different pieces of manufacturing equipment. In-situ operations also lead to a reduction in the number of expensive pieces of manufacturing equipment that an integrated circuit manufacturer must purchase and maintain.
Traditionally, in forming capacitive devices, a deposition of a metal electrode layer is performed in a chamber which is completely separate from a chamber used to deposit a subsequent dielectric layer. Again, a top layer electrode is deposited in a chamber separate from the process used to deposit the dielectric layer. A major concern is that oxidation of one or both electrode layers could occur if all layers were produced in situ, and this could make the electrode films resistive, or destroy their usefulness altogether.
Accordingly, it would be desirable to deposit two or more layers of nonconforming materials in situ, in the same chamber, for the many advantages that such a process would provide. It would further be desirable to use a single precursor material for the deposition formation of at least two layers of nonconforming materials in situ. It would further be desirable to increase the storage density of capacitive devices constructed by such techniques.
SUMMARY OF THE INVENTION
The present invention provides a process for manufacturing a buildup of layers on a semiconductor element, wherein a single precursor material can be used to provide multiple, different layers of the stacked element. A single process chamber may also be used, if desired. The process uses a single precursor element, e.g. tantalum, that can be provided with successively different chemical conditions to produce different layers having specific properties, e.g. a conductive layer follow

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