Precharge system for a semiconductor memory device

Details Precharge system for a semiconductor memory device Precharge system for a semiconductor memory device

1996-11-04

1999-10-26

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365194, 365207, 365193, 365204, G11C 700

Patent

active

059739720

ABSTRACT:
A method for precharging a bit line pair or data line pair in a semiconductor memory device includes generating a precharge pulse signal when a write enable line is deactivated at the beginning of a read cycle. The line pair is rapidly precharged by a pair of large transistors which turn on in response to the pulse signal. The pulse signal ends and turns of the transistors before a word line is enabled during the read cycle to prevent the large transistors from interfering with the bit sensing operation. A precharge circuit for precharging a bit line pair or data line pair in a semiconductor memory device includes a pulse generator having a delay circuit that determines the pulse width of a precharge pulse which is generated when a write enable line is deactivated. A write and precharge circuit includes two large transistors connected between a line pair and a power source that turn on and rapidly precharge the line pair during the precharge pulse. A third large transistor is connected between the lines of the line pair to equalize the voltages of the lines when the precharge pulse is generated.

REFERENCES:
patent: 5506805 (1996-04-01), Hirose et al.
patent: 5579256 (1996-11-01), Kajigaya et al.

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