Precharge circuit for use in a semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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36518907, G11C 1140

Patent

active

048520640

ABSTRACT:
A precharge circuit for use in a static random access memory is disclosed two step bit line pair precharging scheme in a precharge cycle performed prior to a read operation. The first precharging step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step is performed via means for precharging more dominantly than the transistor pair in response to a second pulse generated by the address transition detection circuit. Owing to the off-state of the N-channel MOS transistor pair in a read operation after a write operation, high speed read operation is obtained.

REFERENCES:
patent: 4743784 (1988-05-01), Ohara et al.

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