Power reduction in scannable D-flip-flop with synchronous...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C711S109000

Reexamination Certificate

active

06986089

ABSTRACT:
In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

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patent: 6763489 (2004-07-01), Nadeau-Dostie et al.
“Token Scan Cell for Low Power Testing” Huang et al. Electronics Letters Publication Date: May 24, 2001, pp. 678-679 vol.: 37, Issue: 11 ISSN: 0013-5194 Inspec Accession No.: 6952438.
“A Token Scan Architecture for Low Power Testing” Huang et al. International Test Conference Proceedings, Publication Date Oct. 30-Nov. 1, 2001 pp. 660-669 Inspec Accession No.: 7211374.
“An Analysis of Power Reduction Techniques in Scan Testing” by Saxena et al. International Test Conference Proceedings, 2001 Publication Date: Oct. 30-Nov. 1, 2001 pp. 670-677 Inspec Accession No.: 7211375.
“Peak-Power Reduction for Multiple-Scan Circuits During Test Application” by Lee et al. Proceedings of the Ninth Asian Test Symposium, 2000. Publication Date: Dec. 4-6, 2000, pp. 453-458 Inspec Accession No.: 6846367.

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