Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-10
2006-01-10
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C711S109000
Reexamination Certificate
active
06986089
ABSTRACT:
In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.
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Hill Anthony M.
Simpson Richard D.
Brady III W. James
Britt Cynthia
Lamarre Guy
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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