Power management circuit

Details Power management circuit Power management circuit

2006-11-07

2006-11-07

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S126000, C326S127000

Reexamination Certificate

active

07132848

ABSTRACT:
A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of data signal outputs, a first PMOS transistor and a second PMOS transistor. A first switch is coupled between a power voltage, the power control signal and the logic cell. A latch circuit coupled between the power voltage and the data signal outputs preserves the voltage levels respectively of the complementary pair of data signal outputs when the logic cell operates in the standby mode.

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“Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems” Lai et al.; 1997, no date.
USPTO Office Action mailed Dec. 14, 2005 for U.S. Appl. No. 10/899,320, filed Jul. 26, 2004.

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