Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
1999-12-23
2001-10-09
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S154000
Reexamination Certificate
active
06301174
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to reading from computer memory. More particularly, the present invention relates to conserving power during memory read operations.
BACKGROUND OF THE INVENTION
A common operation in computer processing is reading a data value from memory, such as a random access memory (RAM). A single RAM cell typically holds the value of a single data bit, a zero or a one. Most memory chips arrange the RAM cells in arrays of 2
n
by 2
m
bits. The 2
n
rows may be efficiently accessed an entire row at one time, and a column decoder then selects one word of 2
k
bits out of 2
m
in the row, to read, corresponding to 2
k
individual RAM cells. An entire word is typically retrieved from RAM and some systems may read each of the word bits instead of selectively reading only a few bits. Since in many instances each bit in the word will be needed, it is often more efficient to read the entire row than to incur the overhead of specifying individual bits and only reading those specified. However, there may be instances when not every bit in a particular word is needed.
Although there are many possible circuit designs for an individual RAM cell, and the present invention is not intended to be limited to any particular RAM design, a common technique for reading a value from RAM is to first precharge a bit line and then to sense, or read the RAM value. The precharge operation typically involves “pulling up” one or more bit lines to a voltage level corresponding to a logical “one”. Following the precharge, one or more access transistors may allow the bit line(s) to interact with the RAM cell. The precharged bit line may then be conditionally discharged based on the data value stored in the RAM cell. Thus, the interaction of the precharged bit line(s) and the RAM value may be used to read the RAM value.
Whether the precharge discharges on a zero or a one stored in a RAM cell depends on the circuit used, and the present invention is not intended to be limited to any particular RAM read circuit. However, for one of the two data states, the precharge is discharged. As will be explained more fully below, there are situations where it may be advantageous to avoid discharging the precharge so that subsequent read operations do not have to pull up, or charge, the bit line. The present invention avoids discharging the precharge in these instances, and in doing so conserves the power needed to fully precharge the bit line on subsequent read operations.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the invention, unused data bits are set to a preferred value, either zero or one, depending on the circuit used to read the data. With the unused data bits set to the preferred value the precharge is not discharged during the data read operation. Not discharging the precharge allows power to be saved in the precharge and read operation.
REFERENCES:
patent: 5493536 (1996-02-01), Aoki
patent: 5754485 (1998-05-01), Miura
patent: 5870331 (1999-02-01), Hwang et al.
patent: 6078544 (2000-06-01), Park
patent: 6091629 (2000-07-01), Osada et al.
patent: 6097651 (2000-08-01), Chan et al.
Ho Hoai V.
Intel Corporation
Kenyon & Kenyon
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