Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-20
2003-04-08
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S634000, C438S656000
Reexamination Certificate
active
06544829
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to improving gate functionality in metal oxide semiconductor field effect transistors.
BACKGROUND
Integrated circuits, such as CMOS devices, typically use polysilicon as the preferred gate electrode material. The polysilicon gates are typically doped to increase their conductivity. For example, a PMOS gate is generally doped with p+ dopants, and an NMOS gate is typically doped with n+ dopants.
As the device dimensions of integrated circuits have been continually reduced, new issues in regard to device operation and reliability have arisen. Devices manufactured with deep submicron dimensions tend to be more powerful and faster, but tend to require a thinner gate oxide to provide sufficient current drive as the supply voltage is scaled down. As the gate oxide thickness decreases, issues such as gate depletion become more of a problem and create additional constraints, often with competing interests, on fabrication parameters such as gate doping and annealing conditions.
For example, the gates of an integrated circuit are often doped at the same time as the source and drain regions of the device. However, as the gate oxide is reduced in thickness, this standard practice tends to have competing interests. If the dopant level and the anneal temperature are relatively low, then active dopant concentration at the interface between the gate electrode and the gate dielectric also tends to be relatively low, resulting in a depletion of the dopant in the gate electrode near the gate dielectric when the channel is inverted, especially when a relatively strong bias is applied. In such a situation the conduction band in the gate depletion region tends to bend, causing a voltage drop and an effective reduction in gate voltage, which reduces the current drive through the channel.
On the other hand, if the effective dopant level in the gate electrode is increased such as with a higher implant dose or anneal temperature, the implanted and activated dopant tends to penetrate the gate oxide and enter the channel region. This situation tends to cause charge trapping in the gate oxide and variations in the threshold voltage. The problems caused by these competing issues of gate depletion and dopant penetration tend to increase as gate oxide thickness is decreased.
What is needed, therefore, is a method of fabricating an integrated circuit with a CMOS compatible process flow, where the problems of gate depletion and dopant penetration are reduced.
SUMMARY
The above and other needs are met by a method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region.
The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.
In this manner, a substantially completely silicided gate electrode is formed in a relatively standard CMOS process flow. A hard mask is used to define the polysilicon gate electrode precursor, which is often done in a standard CMOS process flow. However, the unpatterned polysilicon layer is deposited to a thickness that can be substantially consumed in the later silicide process, rather than to some other thickness, and the hard mask is left in place during the source drain dopant implant. The combined thickness of the hard mask and the polysilicon layer is sufficient to prevent the dopant implant from entering the gate oxide below the gate area. Thus, the substantially completely silicided gate removes the problems associated with dopant depletion during operation of the gate, and the combined thickness of the hard mask and the polysilicon layer during gate dopant implant reduces and preferably eliminates any dopant concentration in the gate oxide.
In various preferred embodiments of the invention, the combined first thickness of the hard mask material and the second thickness of the unpatterned polysilicon layer are sufficient to prohibit the dopant from penetrating the first portions of the gate oxide layer. The thickness of the metal layer is preferably just sufficient to substantially completely consume the thickness of the polysilicon gate electrode precursors and form silicide gate electrodes during the annealing step. The thickness of the unpatterned polysilicon layer is preferably between about three hundred angstroms and about four hundred angstroms, the thickness of the hard mask material is preferably between about three hundred angstroms and about eight hundred angstroms, and the thickness of the metal layer is preferably between about one hundred angstroms and about two hundred angstroms.
The hard mask material is preferably formed of a material such as at least one of silicon nitride, silicon oxide, and silicon oxynitride, and most preferably silicon nitride, and the metal layer is formed of at least one of cobalt, nickel, titanium, platinum, and tantalum. The unpatterned polysilicon layer is doped in varying embodiments to tailor the work function of the silicide gate electrodes, at a point during processing that includes one or more of prior to formation of the hard mask material, prior to the deposition of the metal layer, and after formation of the silicide gate electrodes.
REFERENCES:
patent: 4656731 (1987-04-01), Lam et al.
patent: 6127212 (2000-10-01), Chen et al.
patent: 6133128 (2000-10-01), Das et al.
patent: 6214656 (2001-04-01), Liaw
Travel et al.,Totally Silicided(CoSi2)Polysilicon: a novel approach to very low-resistive gate(~2 ohms/square)without metal CMP nor etching, IEEE, 2001.
Gopinath Venkatesh
Kamath Arvind
May Charles E.
Mirabedini Mohammad
Chaudhari Chandra
LSI Logic Corporation
Luedeka Neely & Graham PC
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