Poly-etching method for split gate flash memory cell

Details Poly-etching method for split gate flash memory cell Poly-etching method for split gate flash memory cell

2006-09-05

2006-09-05

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

07101758

ABSTRACT:
A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.

REFERENCES:
patent: 6426524 (2002-07-01), Lam et al.
patent: 2004/0201059 (2004-10-01), Ding

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