Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-23
2004-04-20
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S397000
Reexamination Certificate
active
06724053
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods for manufacturing transistors and integrated circuit devices comprising multiple transistors. In particular, the invention relates to p-type metal-oxide-semiconductor (PMOS) devices and methods for manufacturing such devices. The invention relates most particularly to field effect transistor (FET) devices, including PMOSFET devices, and the manufacture of such devices. The invention comprehends both discrete PMOS devices, or PMOS devices included in integrated circuit devices.
BACKGROUND OF THE INVENTION
There are two major types of FET devices, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate, and source and drain regions formed in a substrate. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns “on” and current may flow between the source and drain regions.
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an “on” state and an “off state.”
In recent years, the computer industry has experienced extremely rapid growth in all aspects, including number of units produced, breadth of applications, power and speed of operation, and complexity of competing machines. This growth is attributable to many factors, including remarkable increases in the number of active devices (typically transistors) included in the integrated circuit devices used in computers. By increasing the number of transistors in an integrated circuit device, the size of a computer may be reduced, or a more complex computer may be made within a particular computer case size. In addition, by increasing the number of transistors in an integrated circuit device, operational problems such as cross talk between physically adjacent conductors and signal propagation delays between different sections of the computer can be reduced. Further, integrated circuit devices are typically less expensive and more reliable than counterparts manufactured from discrete components. For these and many other reasons, the use of integrated circuit devices of increasing size and complexity has become the standard of the computer industry.
The trend toward more complex integrated circuit devices has resulted in increasing density of individual devices within the integrated circuit devices. To increase the number of individual devices within an integrated circuit, it is necessary to decrease the size of each individual device. The size of individual devices cannot be reduced arbitrarily. There are limitations to size reduction, including dimensional tolerance capabilities associated with manufacturing processes and various electrical phenomena that are associated with physical dimensions of the device. In addition, the essential need for high reliability of integrated circuit devices places limitations on shrinking the size of such devices. The steps of identifying these and other limitations and discovering techniques for ameliorating these limitations have made possible the increasing complexity of integrated circuit devices.
The prior art in the field of manufacture of PMOS devices has numerous examples of identification of problems that occur during manufacture and subsequent usage of such devices. The art also has examples of proposed solutions to the identified problems. A brief summary of some of the relevant patent art is provided below.
U.S. Pat. No. 4,420,872 issued to Soledad de Zaldivar teaches the use of nitrogen ion implantation to create a silicon nitride-containing layer as a mechanism to mask FET devices against undesired silicon oxidation during manufacture. U.S. Pat. No. 4,774,197 issued to Haddad et al. teaches the use of nitrogen ion implantation into the polycrystalline silicon gate of an FET which, during subsequent high-temperature causes a formation of silicon nitrides at the interface between the gate and the underlying gate insulation, and at the interface between the gate insulation and the underlying silicon substrate. This structure makes the gate insulation more nearly defect-free and more reliable in service.
U.S. Pat. No. 5,330,920 issued to Soleimani et al. teaches the use of nitrogen ion implantation as a mechanism to control gate oxide layer thickness. The patent teaches growing a sacrificial oxide layer on the surface of a silicon substrate, implanting nitrogen into the substrate through the sacrificial layer, removing the sacrificial layer, then growing a gate oxide layer. Where the nitrogen had been previously implanted into the substrate, the rate of gate oxide layer growth is reduced.
U.S. Pat. No. 5,468,657 issued to Hsu and U.S. Pat. No. 5,589,407 issued to Meyyappan et al. each teach the use of nitrogen ion implantation in conjunction with the growth of buried oxide layers that comprise the insulator in silicon-on-insulator (SOI) wafers used in manufacturing complementary metal-oxide-semiconductor (CMOS) devices. U.S. Pat. No. 5,908,312 issued to Cheung et al. teaches the implantation of atomic nitrogen into the silicon substrate before the growth of an oxide gate insulating layer. The patent specifically states that atomic nitrogen is the preferred species for this purpose, as opposed to molecular nitrogen.
Five recent patents, assigned to a common assignee, have taught the importance of threshold voltage in MOS transistor devices, and have described ways to control that voltage. These five patents are U.S. Pat. Nos. 5,674,788; No. 5,893,739; No. 5,909,622; No. 5,851,893; and No. 5,861,335. In the first of these patents, Wristers et al. teach that an oxynitride gate insulation layer reduces the likelihood of diffusing boron from the gate into the channel region lying below the gate. The oxynitride layer also reduces the trapping of electrons in the gate insulator. Wristers et al. also teach that the oxynitride layer is advantageously grown in situ by using a growth atmosphere that contains nitrous oxides, nitric oxides, or both.
The next two patents describe the deleterious effects of hot carriers, whether holes or electrons, that can accumulate in the gate oxide layer and raise the threshold voltage of the MOSFET device. The transistors produced according to the of these two patents feature asymmetrical construction, with a wider barrier between the gate and drain than between the gate and source. Gardner et al. teach a mechanism to control hot carrier effects by injecting barrier atoms into the silicon beneath the gate edge near the drain. Hause et al. teach implanting nitrogen into the silicon substrate on either side of the channel region, where such implantation is done concurrently or after the doping of the source and drain regions.
The existence of a threshold voltage is an inherent characteristic of MOSFET devices. In the case of a PMOSFET, a high threshold voltage signifies that the device is readily turned “on,” meaning that holes flow from the source to the drain. A practical consequence of a high threshold voltage is that the PMOSFET has a greater current-driving capability, which implies a higher speed of logic level transitions. Thus, high threshold voltages in PMOSFET devices are desirable to increase the operating speed of digital circuits. Conversely, a high threshold voltage increases the susceptibility of the device to current flow between the source and drain when the gate voltage is less than the threshold voltage; that is when the device operates in a sub-threshold regime. Also, a PMOSFET having a high threshold voltage typically has less immunity to electrical noise and has higher contribution to the chi
Divakaruni Rama
Katsumata Ryota
La Rosa Giuseppe
Rengarajan Rajesh
Weybright Mary E.
RatnerPrestia
Schnurmann H. Daniel
Vu Hung
LandOfFree
PMOSFET device with localized nitrogen sidewall implantation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with PMOSFET device with localized nitrogen sidewall implantation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PMOSFET device with localized nitrogen sidewall implantation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3191482