Electricity: electrical systems and devices – Electric charge generating or conducting means – Use of forces of electric charge or field
Reexamination Certificate
2011-07-19
2011-07-19
Patel, Dharti H (Department: 2836)
Electricity: electrical systems and devices
Electric charge generating or conducting means
Use of forces of electric charge or field
Reexamination Certificate
active
07983018
ABSTRACT:
An arrangement for securing a wafer during substrate processing is provided. The arrangement includes a power supply and an electrostatic chuck (ESC). The ESC supports the wafer and includes a positive and a negative terminal. A positive high voltage is provided to the positive terminal through an RF filter and a negative high voltage is provided to the negative terminal through the RF filter. The arrangement also includes a first and a second trans-impedance amplifiers (TIAs) that measure a first set of voltages for determining a value of a positive load current applied to the positive terminal and a third and fourth TIAs that measure a second set of voltages for determining a value of a negative load current applied to the negative terminal. The arrangement yet also includes a program to adjust a bias voltage using the values of the positive load current and the negative load current.
REFERENCES:
patent: 5103367 (1992-04-01), Howitz et al.
patent: 6518195 (2003-02-01), Collins et al.
patent: 6563076 (2003-05-01), Benjamin et al.
patent: 7166233 (2007-01-01), Johnson et al.
patent: 7169255 (2007-01-01), Yasu et al.
patent: 7768766 (2010-08-01), Jafarian-Tehrani et al.
patent: 2005/0225923 (2005-10-01), Howald
patent: 2006/0221540 (2006-10-01), Himori et al.
patent: 2008/0144251 (2008-06-01), Tao
patent: 2008/0218931 (2008-09-01), Hsu et al.
“U.S. Appl. No. 11/770,606”, filed Jun. 28, 2007.
“International Search Report”, Issued in PCT Application No. PCT/US2008/065369; Mailing Date: Sep. 30, 2008.
“Written Opinion”, Issued in PCT Application No. PCT/US2008/065369; Mailing Date: Sep. 30, 2008.
“International Preliminary Report on Patentability”, Issued in PCT Application No. PCT/US2008/065369; Mailing Date: Dec. 10, 2009.
“Notice of Allowance and Fees Due”, U.S. Appl. No. 11/770,606, Mailing Date: Mar. 25, 2010.
Jafarian-Tehrani Seyed Jafar
Lu Ralph Jan-Pin
IP Strategy Group, P.C.
Lam Research Corporation
Patel Dharti H
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