Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2000-07-20
2003-09-09
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S712000
Reexamination Certificate
active
06617253
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly, to a plasma etching method using selective polymer deposition and a method of forming a contact hole using the plasma etching method.
2. Description of the Related Art
As the integration density increases, fabrication of semiconductor devices becomes complicated and individual semiconductor devices formed on a substrate have become finer patterns. Photolithographic processing necessarily requires the development of a new photoresist suitable for forming finer patterns.
Generally, the integration of semiconductor devices requires a reduction in the line width of a via hole formed in order to connect conductive material layers having an interlayer dielectric layer therebetween, or the width of a contact hole formed to expose some region of a substrate. The width of a via hole or a contact hole is determined by the line width of a photoresist pattern.
As stated above, with the increase of the integration density of semiconductor devices, it becomes difficult to form a contact hole or via hole using a conventional photolithograhgic process, because the contact hole to be formed becomes smaller than the resolution limit of the optical system, and also because formation of a photoresist pattern having a desired profile becomes difficult.
A method using an exposure beam having a short wavelength to improve the resolution upon the formation of a photoresist pattern is well known as a method for forming a fine pattern.
For example, there is proposed a method using a KrF excimer laser with a 248 &mgr;m wavelength instead of an existing i-line laser with a 365 &mgr;m wavelength as a light source for exposure to fabricate a 256 M-bit dynamic random access memory (DRAM) with a 0.25 &mgr;m design rule.
Also, a beam having a shorter wavelength than the KrF excimer laser must be used to fabricate a 1 G-bit DRAM under a 0.2 &mgr;m design rule using a high-level fine patterning technique. In order to achieve this object, an ArF excimer laser having a 193 nm wavelength is used as a light source for exposure.
However, deep UV rays having a very short wavelength for this ultra-fine pattern processing, or KrF or ArF excimer laser light is highly absorbed by a photoresist film upon exposure. Hence, if a thick photoresist film is formed, light cannot reach the bottom of the photoresist film.
Accordingly, if ArF excimer laser having a short wavelength of 300 nm (=0.3 &mgr;m) is used as a light source for exposure to achieve high resolution patterning, a photoresist must be formed to have a thickness of 3000 Å (=0.3 &mgr;m) or less, considering the beam absorption.
However, such a thin photoresist pattern is not resistant to etching when a silicon oxide film below the photoresist pattern is etched. That is, the silicon oxide film below the photoresist pattern has a low selectivity with respect to the photoresist pattern. Thus, the thin photoresist pattern has a limit in acting as an etch mask, which restricts the depth of the silicon oxide film to be etched.
FIGS. 1A through 1C
are cross-sectional views to explain a failure due to an insufficient selectivity with respect to a photoresist pattern when a contact hole is formed by etching a dielectric film using a conventional ArF photolithographic process.
Referring to
FIG. 1A
, a silicon oxide film
11
is formed as an interlayer dielectric layer on a semiconductor substrate
10
. A photoresist pattern
13
is formed thin in order to maximize the resolution upon formation of a fine contact hole. In this case, the photoresist pattern
13
which is used as a mask is not thick enough to sufficiently etch the silicon oxide film
11
to a required depth, when forming deep contact holes.
As shown in
FIG. 1B
, the thickness of the photoresist pattern
13
is also reduced to form a photoresist pattern
13
′, when the silicon oxide film
11
is etched under the conventional silicon oxide film anisotropic etching conditions.
Referring to
FIG. 1C
, when etching is continued in this state to obtain a desired contact depth, part of the photoresist on the periphery of the upper portion of a contact hole is etched, such that the photoresist
13
can no longer sufficiently acts as an etch mask. Thus, the profile of the contact hole becomes inferior.
When a self-aligned contact hole is formed, an interlayer dielectric layer on a gate pattern is etched. And a capping layer, typically formed of silicon nitride, covers a gate electrode acting as a mask for preventing the gate electrode from being exposed during etching of the interlayer dielectric layer. When a deep contact hole is formed using ArF photolithography to obtain high resolution, a very high etch selectivity between a silicon oxide film SiO
2
used as an interlayer dielectric layer and a silicon nitride film Si
3
N
4
used as a capping layer is required.
However, the current etch selectivity has a limit, such that a structural method such as increasing the thickness of the capping layer or forming a thin gate electrode must be used to prevent the gate electrode from being exposed when a deep contact hole is formed.
FIGS. 2A and 2B
are cross-sectional views for illustrating a failure due to an insufficient etch selectivity of an interlayer dielectric layer with respect to a capping layer when a conventional self-aligned contact hole is formed.
Referring to
FIG. 2A
, a gate dielectric layer
25
is formed on a semiconductor substrate
20
. Then, a gate pattern is formed on the gate dielectric layer
25
. The gate pattern consists of a gate electrode G and a capping layer
29
formed of silicon nitride Si
3
N
4
on the gate electrode G. Next, a silicon nitride Si
3
N
4
film is formed on the semiconductor substrate
20
on which the gate pattern has been formed, and is then anisotropically etched, thereby forming capping spacers
27
. A silicon oxide film SiO
2
21
is formed as an interlayer dielectric film on the the substrate including the capping layer
29
and the capping spacers
27
. A photoresist pattern
23
having a predetermined thickness is formed on the silicon oxide film
21
.
Referring to
FIG. 2B
, the capping layer
29
and the capping spacers
27
are partially etched due to the limit of an etch selectivity of the silicon oxide film
21
with respect to the silicon nitride film when the silicon oxide film is etched to form a self-aligned contact hole, so that the gate electrode G is exposed. This exposure of the gate electrode G causes contact plug charged in a contact hole, and short-circuit the gate electrode G.
A step of simultaneously forming contact holes having different depths is included in a process for manufacturing semiconductor devices.
FIG. 3
is a cross-sectional view illustrating where the profile of a contact hole becomes undesirable where contact holes having different depths are formed simultaneously.
Referring to
FIG. 3
, a silicon oxide layer
31
, which is an interlayer dielectric layer having a conductive layer pattern
35
formed at a predetermined height therein, is formed on a semiconductor substrate
30
. A photoresist pattern
33
is formed to define contact holes
37
and
39
which expose the conductive layer pattern
35
and the semiconductor substrate
30
, respectively. Next, the contact holes
37
and
39
are formed by etching the silicon oxide layer
31
. At this time, as shown in
FIG. 3
, the photoresist pattern
33
is consumed together with the silicon oxide layer
31
, such that the profile of each of the contact holes
37
and
39
becomes inferior. Simultaneously, the conductive layer pattern
35
fails to act as an etch stop layer by continuous etching performed to form the contact hole
39
, which is deeper than the contact hole
37
. Thus, the conductive layer pattern
35
may be penetrated. In this case, a problem such as an increase in contact resistance can occur.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a plasma etching method
Ahn Tae-Hyuk
Chu Chang-Woong
Jeong Sang-Sup
Kim Ji-Soo
Kunemund Robert
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Umez-Eronini Lynette T.
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