Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-13
2002-11-05
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S246000, C438S249000, C438S255000, C438S386000, C438S389000, C438S392000, C438S398000
Reexamination Certificate
active
06475859
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to the use of plasma doping (PLAD) for a DRAM with deep trenches (DT) in hemispherical grains (HSG) as an alternative to arsenic glass (ASG) doping and gas-phase doping to prevent deformation of narrow trench structures and hemispherical grains, and thereby insure high capacitance.
2. Description of the Related Art
In general, increasing the density of integrated circuit devices is accomplished in part by decreasing the size of the structures within the devices (such as wiring lines and transistor gate widths and by decreasing the separation between the structures which make up the integrated circuit devices).
Reducing the size of circuit structures is referred to as decreasing the “design rules” used for the manufacture of the integrated circuit device. For semiconductor memories of the dynamic random access type, i.e., “DRAMs,” information is stored by varying the amount of charge stored within each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one. Each of the memory capacitors in a typical DRAM has a parallel plate structure. The surface area of the plates of the memory capacitor determines the amount of charge that can be stored on the capacitor, given the fixed operating voltage of a typical memory device, the plate separation that can reliably be manufactured, and the dielectric constant of the capacitor dielectric used in the capacitors.
Reducing the size of a DRAM capacitor in accordance with reduced design rules reduces the surface area of the capacitor plates and therefore has the effect of reducing the amount of charge that can be stored on the memory capacitor.
Plates of memory capacitors must be larger than a minimum size to obtain reliable operation of the memory. For ultra large scale integration (“ULSI”) DRAM designs, bit line capacitances, sense amplifier sensitivities and noise signals are such that further reductions in the amount of charge stored on the DRAM memory capacitors could prevent the information stored on the capacitor from reliably being read out. Because charge inevitably drains from memory capacitors, DRAMs require the periodic refreshing of the charge stored on the capacitors of the DRAM to ensure that the stored charge remains above the minimum detectable level. Further reductions in capacitor size require more frequent refresh operations for the DRAM, which are undesirable because at least portions of the DRAM are unavailable for reading and writing of information during refresh operations.
Therefore, to meet the challenges of reduced design rules, DRAM designs are employed which incorporate capacitors having vertical extensions above the surface of the substrate (i.e., “stacked”) or below the surface of the substrate (i.e., “trenched”). By adopting a more three-dimensional structure via the stacked or trenched designs, these DRAM designs provide memory capacitors having larger capacitances that consume less of the substrate surface area.
Where the stacked capacitor and trench capacitor designs involve more complicated structures, which are more difficult to manufacture, these designs have been adopted with a significant degree of success.
Nevertheless, there additionally remains a need to further increase the capacitance of DRAM storage capacitors while decreasing the amount of surface area consumed by the DRAM storage capacitor on the surface of the semiconductor substrate.
One method for increasing the capacitance for a fixed substrate surface area is to use textured polysilicon as the bottom plate for the memory capacitor. The layer of textured polysilicon is used as the lower electrode for the capacitor, a thin dielectric layer covers the surface of the lower electrode, and a cell plate is formed on the dielectric layer to serve as the upper electrode for the capacitor. By using textured polysilicon as the lower electrode of the capacitor, the surface area of the capacitor is increased without extending the capacitor electrodes laterally, so that the structure has improved capacitance for a fixed surface area.
U.S. Pat. No. 5,753,559 disclose a method for increasing the capacitance of a DRAM storage capacitor by utilizing textured surfaces of plasma deposited grown hemispherical grained silicon (HSG-Si) on polysilicon. The method for making the device comprises providing to a deposition system a substrate having an exposed surface of a conductor comprising silicon; generating a plasma region within the deposition system; providing a reactant gas comprising silicon to the deposition system so that ions comprising silicon are generated within the deposition system and transported to the exposed surface; and depositing a layer of HSG-Si on the exposed surface of the conductor comprising silicon.
A method for roughening and volume expansion of trench sidewalls to form a high capacitance trench cell for high density DRAM applications in disclosed in U.S. Pat. No. 5,877,061. The method entails: forming a trench in a substrate through an opening in a dielectric mask material positioned on the substrate; depositing a conformal layer of silicon containing material over the dielectric etch mask material and into the trench; forming a collar oxide in an upper portion of the trench over the conformal layer of silicon containing material, said collar oxide leaving a lower portion of the trench exposed; and isotropically etching the silicon containing material and the substrate under the silicon containing material in the lower portion of the trench.
Despite the fact that storage capacity or wall surface area in DRAMs have been increased by providing horizontal trenches created in sidewalls; providing porous layers on the trench surfaces; utilizing sidewalls comprising multiple layers which are selectively etched to produce a roughened surface with increased surface area; and doping of a surface layer in a trench with a crystal having a different structure than the material in the surface layer, each of these methods increase production time and processing cost.
Nevertheless, for the sake of providing even higher capacitance when using hemispherical-grained silicon on sidewalls in trenches in a capacitor, it is still essential to achieve very high doping levels in the hemispherical grains, which act as an electrode.
Even though high doping concentrations must be used in the surface layer of trenched sidewalls in hemispherical grains to attain even higher capacitance DRAMS, the achievement of this high doping must unfortunately be done by arsenic glass (ASG) doping and gas-phased doping.
These doping techniques either require the use of very high temperatures that result in a viscous flux of Si that leads to a deformation of trenches and the very small hemispherical grains or are very complicated and not applicable for smaller ground rule devices (i.e., 0.18 &mgr;m or smaller) due to a depletion of source materials and process complexity.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a process for doping of the surface layer of a trench sidewall and hemispherical grains by avoiding the use of arsenic glass (ASG) doping in which the over all process steps are very complicated and not applicable for smaller ground-rule devices of 0.18 &mgr;m or smaller, due to a depletion of source materials and process complexity.
Another object of the present invention is to provide a process for doping the surface layer of trenched sidewall and hemispherical grains without the necessity of using the very high temperatures and long process times required in gas-phase doping techniques that result in viscous flux of Si that cause deformation of trenches and the very small hemispherical grains.
In general, the invention process for doping of trench sidewall and hemispherical grains without the necessity of using the very high temperatures of ga
Hoepfner Joachim
Lee Brian S.
Tews Helmut Horst
Infineon - Technologies AG
Jr. Carl Whitehead
Stanton Braden
Thomas Toniae M.
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