Plasma assisted semiconductor substrate processing chamber...

Details Plasma assisted semiconductor substrate processing chamber... Plasma assisted semiconductor substrate processing chamber...

2000-05-24

2002-04-02

Mills, Gregory (Department: 1763)

Coating apparatus

Gas or vapor deposition

Work support

C118S7230ER, C118S7230IR, C156S345420, C204S298340

Reexamination Certificate

active

06364958

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The present invention relates to a plasma assisted semiconductor substrate processing chamber. More particularly, the invention relates to a plasma assisted semiconductor substrate processing chamber having a plurality of electrically conductive bridges that connect a portion of a substrate support member with a portion of the chamber walls.
2. Description of the Background Art
In plasma assisted semiconductor substrate processing chambers, an electrical discharge, or electrical arcing phenomenon can occur, particularly when a high frequency radio frequency (RF) power source is employed to power a substrate electrode in a substrate support member and when the chamber is large (c.g., capable of processing 300 mm substrates). The electrical arc can cause sputtering of chamber wall material that deposits on and contaminates a substrate that is presently in the chamber or a substrate that is later introduced into the chamber.
For example, arcing has been observed in a plasma assisted chemical vapor deposition (CVD) chamber that is designed to process 300 mm substrates. The chamber has electrically conductive walls that are DC grounded. One RF power source is utilized for plasma generation while another RF power source powers a substrate electrode in a substrate support member to provide substrate biasing during processing. A single electrically conductive bridge connects a grounded portion of the substrate support member with a portion of the grounded chamber walls, providing an RF ground path from the substrate support member to the chamber walls. Within such a chamber, arcing from the plasma to the chamber sidewalls has been observed when the RF power source coupled to the substrate electrode is activated.
Arcing from the plasma to the chamber walls has been determined to be the result of chamber geometry being such that the largest electrical RF return path length exceeds approximately ¼ wavelength of a surface RF wave inside the chamber. According to RF theory, high density, magnetic field-free plasma sources, as may be used in certain CVD chambers, produce plasmas that are opaque to RF fields within a frequency range from 0-200 MHz. For this reason, RF currents flow along the surface of the plasma. In effect, the surface of the plasma forms one electrode and the chamber wall forms another electrode of a waveguide. The width of the waveguide is the width of the plasma sheath and the length of the waveguide is the inner circumference of the chamber. When the largest electrical RF return path length exceeds approximately ¼ of a surface RF wavelength inside the chamber, a standing wave will form “RF nodes”. The RF nodes arise at random locations along the surface of the chamber walls. Extremely high voltage can be created between the RF nodes and a plasma within the chamber, causing an electrical discharge between the plasma and the chamber walls, which is known as electrical arcing or unpopular arcing.
According to surface wave theory, in the presence of a plasma, an RF wave propagated along conductive chamber surfaces takes the form of a surface wave, with its wavelength and phase velocity reduced by a factor of approximately five as compared with free space [Eqs (1,2)]. As stated above, electrical arcing will occur when the largest electrical RF return path exceeds approximately ¼ of a surface RF wavelength inside the chamber. Since the surface RF wavelength in a chamber is approximately ⅕ of the free space wavelength, electrical arcing occurs when the inner circumference of the chamber exceeds approximately (¼)·(⅕) or {fraction (1/20)} of a free space RF wavelength.
The following surface wave theory equation shows that, as discussed above, the RF wavelength and phase velocity along chamber surfaces (i.e., in the waveguide formed between the plasma and the chamber walls) are reduced by a factor of approximately five compared to free space, in the limit of &ohgr;
pe
/&ohgr;>>1, and &dgr;>d,
V
phase
=c
/(&dgr;/
d
+1)
½
  (1)
where:
V
phase
is the RF phase velocity along a conducting surface;
c is the speed of light;
&dgr;=c/&ohgr;
pe
is the RF skin depth, where &ohgr;
pe
is the plasma frequency;
d≡V
te
/&ohgr;
pe
f(V
rf
,T
c
) is the plasma sheath thickness, V
te
is the electron thermal velocity, and f(T
c
,V
rf
) depends on the sheath model and is a function of the electron temperature T
c
and the RF voltage V
rf
.
For Te=5 eV and f(V
rf
,T
c
)=10 (d is 10 times the Debye length),
V
phase
=c
/(&dgr;/
d
+1)
½
≡c/
5  (2)
The Equation (1) and (2) can also be written as:
&lgr;
surface
≡&lgr;
0
/(&dgr;/
d
+1)
½
≡&lgr;
0
/5  (3)
where &lgr;
surface
is the RF wavelength along the chamber walls, and &lgr;
0
is the free space wavelength of the RF signal.
Therefore, where the largest electrical RF return path exceeds approximately ¼ of the surface RF wavelength, or {fraction (1/20)} of a free space RF wavelength inside the chamber, electrical arcing can occur and can cause sputtering of chamber wall material. In chambers with a single conductive bridge leading from a portion of a substrate support member to DC grounded, conductive chamber walls, the largest electrical RF return path is at least about equal to the inner circumference of the chamber wall. Therefore, in such a single bridge chamber, electrical arcing can occur where the inner chamber wall circumference exceeds approximately ¼ of a surface RF wavelength. Furthermore, in a single bridge chamber, electrical arcing can occur if the inner chamber wall circumference exceeds approximately {fraction (1/20)} of a free space RF wavelength.
Electrical arcing has particularly become a problem as larger plasma assisted chambers are being designed and used to accommodate 300 mm diameter substrates. Chambers that accommodate large substrates generally have commensurately larger inner chamber wall circumferences. Therefore, for a given RF power frequency utilized, when the chamber is designed large enough so that the chamber wall inner circumference exceeds approximately ¼ of a surface RF wavelength or approximately {fraction (1/20)} of a free space RF wavelength for the highest frequency RF power employed to power a substrate electrode in a substrate support member, electrical arcing can occur in the chamber.
In addition, in some instances a second or greater harmonic frequency of a surface wave inside the chamber has sufficient energy to lead to RF nodes and cause electrical arcing. Since each numerically greater harmonic has a wavelength half as great as the previous harmonic, the chamber wall inner circumference that might give rise to electrical arcing for each succeeding harmonic is half that of the previous harmonic.
Therefore, a need exists in the art for a plasma assisted semiconductor substrate processing chamber in which electrical arcing caused by surface wave effects is eliminated.
SUMMARY OF THE INVENTION
The present invention provides a plasma assisted semiconductor substrate processing chamber having a plurality of electrically conductive bridges connecting a portion of a substrate support member with a portion of the chamber walls. The plurality of bridges can prevent electrical arcing from occurring, in the chamber, particularly when a high frequency, radio frequency (RF) power source is employed to power a substrate electrode in a substrate support member within a large chamber. In one aspect, the invention provides a plasma assisted chamber having a plurality of electrically conductive bridges connecting a portion of a substrate support member with a portion of the DC grounded chamber walls.


REFERENCES:
patent: 5556501 (1996-09-01), Collins et al.
patent: 6013584 (2000-01-01), M'Saad
patent: 6074488 (2000-06-01), Roderick et al.
patent: 6174370 (2001-01-01), Yoshida
patent: 6176969 (2001-01-01), Park et al.
patent: 6178919 (2001-01-01), Li et al.

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