Pillar devices and methods of making thereof

Details Pillar devices and methods of making thereof Pillar devices and methods of making thereof

2011-03-15

2011-03-15

Luu, Chuong A. (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S237000, C438S328000

Reexamination Certificate

active

07906392

ABSTRACT:
A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

REFERENCES:
patent: 5780908 (1998-07-01), Sekiguchi et al.
patent: 5891778 (1999-04-01), Wen
patent: 5915167 (1999-06-01), Leedy
patent: 5937280 (1999-08-01), Wen
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6083787 (2000-07-01), Lee
patent: 6133149 (2000-10-01), Yeh
patent: 6420215 (2002-07-01), Knall et al.
patent: 6429449 (2002-08-01), Gonzalez et al.
patent: 6525953 (2003-02-01), Johnson
patent: 6750091 (2004-06-01), Gonzalez et al.
patent: 6952043 (2005-10-01), Vyvoda et al.
patent: 7151046 (2006-12-01), Takeda et al.
patent: 7238607 (2007-07-01), Dunton
patent: 7285464 (2007-10-01), Herner et al.
patent: 7737442 (2010-06-01), Yamazaki et al.
patent: 2002/0163027 (2002-11-01), Skotnicki et al.
patent: 2004/0137721 (2004-07-01), Lim et al.
patent: 2004/0157354 (2004-08-01), Kuriyama et al.
patent: 2005/0052915 (2005-03-01), Herner et al.
patent: 2005/0062079 (2005-03-01), Wu et al.
patent: 2006/0189077 (2006-08-01), Herner et al.
patent: 2006/0249753 (2006-11-01), Herner et al.
patent: 2006/0284237 (2006-12-01), Park et al.
patent: 2007/0086235 (2007-04-01), Kim et al.
patent: 2007/0090425 (2007-04-01), Kumar et al.
patent: 2007/0164309 (2007-07-01), Kumar et al.
patent: 2007/0284656 (2007-12-01), Radigan et al.
patent: 2008/0073755 (2008-03-01), Ang et al.
patent: 2008/0078984 (2008-04-01), Park et al.
patent: 2008/0128853 (2008-06-01), Choi et al.
patent: 4-67671 (1992-03-01), None
patent: 6-334139 (1994-12-01), None
patent: 100766504 (2007-10-01), None
patent: WO 2007/067448 (2007-06-01), None
Office Action mailed Dec. 9, 2009 in related U.S. Appl. No. 12/007,780.
Invitation to Pay Additional Fees, including partial International Search Report mailed Apr. 15, 2009, received in corresponding International application No. PCT/US2009/030937 (6 pgs.).
Office action mailed May 27, 2009, received in corresponding U.S. Appl. No. 12/007,780 (8 pgs.).
http://www.clarycon.com/Resources/Slide3t.jpg (1 pg.).
http://www.clarycon.com/Resources/Slide5i.jpg (1 pg.).
A. E. Braun, Architecture Becomes Mainstream, Semiconductor International, vol. 28, No. 4, Feb. 2005, pp. 43-48.
J. Tony Pan et al., “Copper CMP and Process Control”, CMP-MIC 99 Conference (Feb. 11-12, 1999), 7 pgs.
Shuji Ikeda et al., “Process Integration of Single-Wafer Technology in a 300-mm Fab, Realizing Drastic Cycle Time Reduction With High Yield and Excellent Reliability”, IEEE Transactions on Semiconductor Manufacturing, vol. 16, No. 2, May 2003, pp. 102-110.
Jeff Gambino et al., “Thermal Oxidation of Ni and Co Alloys Formed by Electroless Plating”, Materials Research Society, Symposium Proceedings vol. 914, Apr. 18-21, 2006, Abstract No. 0914-F05-09, pp. 173-179.
U.S. Appl. No. 11/819,078, filed Jun. 25, 2007, Herner.
International Search Report and Written Opinion, mailed Jun. 5, 2009, received in International Application No. PCT/US2009/030937.
International Preliminary Report on Patentability, International Application PCT/US2009/030937. International Bureau of WIPO, Jul. 29, 2010.

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