Peripheral gate stacks and recessed array gates

Details Peripheral gate stacks and recessed array gates Peripheral gate stacks and recessed array gates

2005-09-01

2008-08-26

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21651, C438S243000, C438S151000, C438S164000

Reexamination Certificate

active

07416943

ABSTRACT:
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

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