Performance-aware logic operations for generating masks

Details Performance-aware logic operations for generating masks Performance-aware logic operations for generating masks

2008-09-17

2011-11-01

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Layout generation

C438S014000, C700S120000, C382S144000

Reexamination Certificate

active

08051392

ABSTRACT:
A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

REFERENCES:
patent: 5498579 (1996-03-01), Borodovsky et al.
patent: 6189136 (2001-02-01), Bothra
patent: 6327695 (2001-12-01), Bothra et al.
patent: 2008/0005718 (2008-01-01), Green
patent: 2008/0169484 (2008-07-01), Chuang et al.
patent: 2009/0095988 (2009-04-01), Rost
patent: 2010/0187635 (2010-07-01), Beyer et al.

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