Patterning for elliptical Vss contact on flash memory

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S672000, C438S638000, C257S390000, C257S316000, C257S371000

Reexamination Certificate

active

06900124

ABSTRACT:
A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.

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patent: 5636002 (1997-06-01), Garofalo
patent: 5674773 (1997-10-01), Koh et al.
patent: 5973374 (1999-10-01), Longcor
patent: 6515329 (2003-02-01), Lee et al.
patent: 6521522 (2003-02-01), Cho
Levenson et al., “The Vortex Mask: Making 80nm contacts with a twist!”

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