Patterned buried insulator

Details Patterned buried insulator Patterned buried insulator

2000-12-08

2002-08-06

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Implanting to form insulator

C438S407000, C438S440000, C438S520000, C438S526000, C257S506000, C257S510000

Reexamination Certificate

active

06429091

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is that of forming integrated circuits with a buried insulator, e.g. oxide, that is formed in selected areas.
BACKGROUND OF THE INVENTION
The advantages of circuits with buried oxide are well known, as are the problems associated with having the transistor body isolated from the substrate and with the extra cost associated with the long time required to perform the implant.
Extensive work has gone into various schemes for forming body contacts to alleviate the problems, but they all have problems, usually excessive consumption of silicon area.
It has been suggested to implant the oxygen ions in a patterned fashion and subject the wafer to high temperature annealing, but that still has the extra cost associated with the high dose implant and isolation of defects and oxygen precipitates from the device area.
SUMMARY OF THE INVENTION
The invention relates to an integrated circuit having buried insulator formed only under the sources and drains of transistors.
A feature of the invention is the implantation of a dopant species at a dose two orders of magnitude less than is required for oxygen implantation.
Another feature of the invention is the selective etching of the implanted areas after or during the shallow trench etch.
Yet another feature of the invention is the deposition of oxide in the buried etched cavities.


REFERENCES:
patent: 5963817 (1999-10-01), Chu et al.
patent: 6069054 (2000-05-01), Choi
Sylvia S. Tsao, “Porous Silicon Techniques for SOI Structures”, IEEE Circuits and Devices, Nov. 1987, pp 3-7.
Kathy Barla, et al., “SOI Technology Using Buried Layers of Oxidized Porous Si”, IEEE Circuits and Devices, Nov. 1987, pp 11-15.
G. Bomchil, et al., “Porous silicon: The material and its applications to SOI technologies”, Microelectronic Engineering 8 (1988), pp 293-310.
T. Skotnicki, et al., “Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS”, 2000 Symposium on VLSI Technology Digest of Technical Papers, pp 156-157.

Affiliated with

Also associated with

Rating

Patterned buried insulator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Patterned buried insulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Patterned buried insulator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2930930