Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2011-05-10
2011-05-10
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S506000, C438S514000, C438S527000, C257SE21334, C257SE21336, C257SE21337
Reexamination Certificate
active
07939418
ABSTRACT:
Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones. Then, dopant ions are implanted into the first implantation zone at a first density, into the second implantation zone at a second density different from the first density, and into the third implantation zone at a third density that is a midway value between the first and second densities.
REFERENCES:
patent: 5281542 (1994-01-01), Hui et al.
patent: 6005272 (1999-12-01), Gardner et al.
patent: 6027989 (2000-02-01), Poole et al.
patent: 6037629 (2000-03-01), Gardner et al.
patent: 6049481 (2000-04-01), Yamasaki
patent: 6229148 (2001-05-01), Prall et al.
patent: 6255178 (2001-07-01), Brown et al.
patent: 7105839 (2006-09-01), White
patent: 7365406 (2008-04-01), Rouh et al.
patent: 2002/0005553 (2002-01-01), Ootsuka et al.
patent: 2002/0185686 (2002-12-01), Christiansen et al.
patent: 2007/0023696 (2007-02-01), Lee
patent: 2007/0082450 (2007-04-01), Van Dal et al.
patent: 1564313 (2005-01-01), None
patent: 1868046 (2006-11-01), None
patent: 2002-170515 (2002-06-01), None
patent: 10-2003-0035946 (2003-05-01), None
patent: 10-2005-0083538 (2005-08-01), None
patent: WO-2005/038900 (2005-04-01), None
Lee Min Yong
Rouh Kyoung Bong
Sohn Yong-Sun
Hynix / Semiconductor Inc.
Lindsay, Jr. Walter L
Marshall & Gerstein & Borun LLP
Pompey Ron
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