Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-07
2006-03-07
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S754090, C716S030000
Reexamination Certificate
active
07010733
ABSTRACT:
A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is also used to apply parametric external I/O tests to the ASIC's functional I/O. The parametric tests are banked into pin groups and applied on the same low pin count tester used for the internal logic tests.
REFERENCES:
patent: 4348759 (1982-09-01), Schnurmann
patent: 4857774 (1989-08-01), El-Ayat et al.
patent: 5068603 (1991-11-01), Mahoney
patent: 5243274 (1993-09-01), Kelsey et al.
patent: 5253255 (1993-10-01), Carbine
patent: 5369643 (1994-11-01), Rastgar et al.
patent: 5412260 (1995-05-01), Tsui et al.
patent: 5513186 (1996-04-01), Levitt
patent: 5563830 (1996-10-01), Ishida
patent: 5712858 (1998-01-01), Godiwala et al.
patent: 5734660 (1998-03-01), Fujisaki
patent: 5909450 (1999-06-01), Wright
patent: 6046947 (2000-04-01), Chai et al.
patent: 6448796 (2002-09-01), Ellison et al.
patent: 6556938 (2003-04-01), Rohrbaugh et al.
patent: 6658613 (2003-12-01), Rearick et al.
patent: 0388790 (1990-09-01), None
“A Study of the Optimization of DC Parametric Tests” Chang, J.M. International Test Conference 1990 Proceedings: Sep. 10-14, 1990 pp. 478-487 Inspec Accession No.: 3976214.
Arimilli et al., “Method to Verify Chip-to-Chip Interconnect Within a Hardware System” IBM Technical Disclosure Bulletin, Vo. 36, No. 06A, Jun. 1993, pp. 437-438.
A. D. Savkar, “N-Way Testpoint for Complex LSI Design”, IBM Techinical Bulleting, vol. 14, No. 10, Mar. 1972, pp. 2937-2938.
Bassett Robert W.
Christensen Garrett S
Combs Michael L.
Farnsworth L. Owen
Gillis Pamela S.
Britt Cynthia
Canale Anthony J.
De'cady Albert
Walsh Robert A.
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