Parallel testing of a multiport memory

Details Parallel testing of a multiport memory Parallel testing of a multiport memory

2000-02-22

2004-01-20

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06681358

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital electronic memory devices, and in particular to an efficient method and apparatus for testing multiport memories.
2. Description of the Related Art
It is common practice for the manufacturers of memory chips to test the functionality of the memories at the manufacturing site. After the chips have been tested and certified for shipment, upon sale to the users, the users generally depend upon the reliability of the chips for their own systems to function properly. As the line width of memory cells within a memory array circuit chip continue to shrink (now at less than half a micron), this reliability becomes more difficult to achieve. One of the challenges for the manufacturers of memory devices, is to increase memory capacity without decreasing chip yields due to malfunctioning parts.
Before the memory chips are released for shipment, they typically undergo testing to verify that the support circuitry for the memory array and each of the memory cells within the memory array is functioning properly. This testing is routinely done because it is not uncommon for a significant percentage of the memory cells within the chip to fail, either because of manufacturing defects or degradation faults.
One standard way for testing chip memories involves using an external memory tester, or Automatic Test Equipment (ATE), at the manufacturing site. An external memory tester supplies power and applies test patterns to the chip to detect faults. External memory testers can only test a limited number of chips at a time, and the test speed is limited by the external bus speed. Consequently, this method of testing is expensive, both in terms of equipment costs and time requirements.
Partly to address these issues, and partly to provide off-site testing, built-in self-test (BIST) units have been incorporated into memory chips as a matter of course. Automated test equipment can now be simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the memory chip, and to monitor a single output signal from the chip. The on-board BIST unit generates all the test patterns and asserts the output signal if the chip passes the functionality test. The BIST can be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
The BIST unit operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a BIST unit writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the BIST unit is able to determine whether the memory cell is faulty. Since the functionality of a cell may depend on the data values stored by neighboring cells or the data values carried on nearby bit and word lines, verifying complete cell functionality is a highly combinatorial problem that requires an impractical amount of time for large memories.
However, it has been recognized that certain faults are more common and easier to detect than others. These include: unlinked memory cell faults such as “stuck-at” faults, transition faults, and data retention faults; simple-coupling cell faults such as inversion faults, idempotent faults, bridging faults, state faults, and disturbance faults; addressing faults and read/write faults. Less common and more difficult to detect are linked faults, neighborhood pattern sensitive faults, and complex coupling faults, all of which involve three or more memory cells. These and other faults are described at length in co-pending U.S. patent application Ser. No. 09/363,697, filed Jul. 28, 1991, which is hereby incorporated herein by reference. In the interest of practicality, BIST algorithms are typically designed to screen for only certain types of faults.
Several classes of fault detection methods are well known, as illustrated by E. R. Hnatek in “4-Kilobit Memories Present a Challenge to Testing”,
Computer Design, May
1975, pp. 117-125, which is hereby incorporated herein by reference. As Hnatek discusses, there are several considerations that should be taken into account when selecting a fault detection method, including fault coverage and length of the test procedure. Also, since no practical method provides complete coverage, the suitability of the various methods for detecting particular types of faults should be considered. The most popular class of fault detection methods is represented by the March C algorithm and its variants such as March C−, March C+, Smarch, or March L R.
With multiport memories, the likelihood of shorts or excess coupling between word lines or bit lines increases substantially relative to single port memories. Ideally, one port can access any row of cells while another port is accessing another row of cells without interference between the two ports, since the ports do not share word lines and bit lines. In reality, however, manufacturing defects can cause one port to interfere with another port, affecting the data values that are read or written through either port. Consequently the various ports need to be exercised simultaneously to verify functionality. Existing methods include: (1) the Single Port BIST method, (2) the Shadow Read method, and (3) the Dual Port method. In addition to these methods, other methods exist. However,these other methods require one or more modifications of the memory array circuitry, which is generally considered to be undesirable.
The Single Port BIST method simply conducts a standard single port BIST through one port while disabling the other ports. This BIST is then repeated for each of the other ports in turn. The standard single port BIST is then repeated. This method ignores the potential for interport faults.
The Shadow Read method is similar to the Single Port BIST method. However, instead of disabling the other ports, a “shadow” read operation is conducted on these ports concurrently with each of the BIST operations through the current test port. Although the data read from these ports is discarded, these read operations get the bit lines for these ports to carry data complementary to the data on the bit lines of the test port. Shorts between the bit lines of different ports can thereby be detected. Unfortunately, only one port at a time is exercised relative to other ports, so that the test time increases in proportion with the number of various combinations of adjacent bit lines.
The Dual Port method is directed toward two port memories. Two BIST operations are run simultaneously, with one port starting at the lowest address and progressing upward, and the other port starting at the highest address and progressing downward. While an existing single-port BIST circuit may be adapted to implement this operation (by complementing the address of the first port to generate the address of the second port), many memory topologies will have the concurrent memory accesses occurring in different columns, so that shorts between bitlines are not detected.
Consequently, these techniques are inadequate. A need exists for a multiport BIST technique that is fast, exhibits good coverage, and requires a minimum of additional complexity relative to a single port BIST.
SUMMARY OF THE INVENTION
Accordingly, there is disclosed herein a multiport BIST method advantageously based on adapting a single port BIST method by dividing the memory into sections based on the number of ports and applying the single port BIST simultaneously through all ports simultaneously (inverting where appropriate), so as to test the sections in parallel. In one embodiment of the invention, an integrated circuit device comprises a multiport memory and a built-in self-test (BIST) unit that applies a first test pattern of read and write operations to a first port of the memory and applies a second test pattern of read and write operations to a second port of the memory. The addresses in the

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