Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2000-08-23
2004-01-20
Vo, T. M (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S305000, C710S012000, C710S020000, C710S035000
Reexamination Certificate
active
06681277
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-238774, Aug. 25, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus and a data transfer control method and, more particularly, to a data processing apparatus for processing various kinds of data, such as audio/video data, other data and programs, and a data transfer control method applied to the data processing apparatus.
Recently, as the computer technology is advancing, various types of digital information device, such as multimedia-handling personal computers, set-top boxes, digital TVs and game machines, have been developed. There has been a demand for a capability to handle various kinds of media, such as broadcasting media, communication media and storage media, in digital information devices of this type.
Accordingly, people are demanding that personal computers should be provided with a function of processing AV (Audio/Video) stream data that needs real-time processing in addition to functions of processing ordinary programs. For consumer AV machines, such as set-top boxes, digital TVs and game machines, there has been a demand for a function of processing computer data, i.e., data other than A/V stream data, and programs, in order to adapt the machines to software-controlled interactive title playback or the like.
Because the bus architecture of conventional computers handle an AV stream and computer data as the same type, however, they are inadequate to feed AV streams that demand highly real-time processing. When a traffic of computer data becomes suddenly heavy while AV stream data and computer data are flowing on the bus at the same time (e.g., at the time of printing or accessing to a file), the AV stream data brings about a significant transfer delay. The reason is as follows. AV stream data and computer data are not distinguished from each other when they are transferred on the bus and thus it is not possible to perform a process of causing AV stream data, which needs real-time processing, flow first by priority.
Even though priority is given only to the transfer of AV stream data, a band sufficient for real-time transfer of AV stream data cannot be necessarily secured when a plurality of items of AV stream data flow on the bus simultaneously, such as when digital broadcast data is stored and displayed simultaneously while it is being received. If, furthermore, an event which needs fast processing occurs at the time of an insufficient band, a process for that event to be executed using programs will be delayed greatly.
Conventional AV machines physically accomplish peer-to-peer connection of devices that handle AV streams by connecting a plurality of devices in the processing order of the AV streams. Therefore, AV streams are not basically input to a CPU. The recent appearance of media (hyper media), which has AV streams and interactive commands integrated, demands that a CPU should process streams. This makes the present physical peer-to-peer connection of devices difficult, and studies on bus connection have started.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a data processing apparatus and a data transfer control method which are capable of efficiently transferring data on a bus.
Another object of the present invention is to provide a data processing apparatus and a data transfer control method which are suitable for integration of AV streams and computer data.
In order to resolve the above objects, a data processing apparatus according to a first aspect of the present invention, comprises a bus used for data transfer; a plurality of nodes connected to the bus and capable of sending/receiving data; and mode selection means having a first bus access mode for transferring data in synchronization with one of rising and falling edges of a clock and a second bus access mode for transferring data in synchronization with each of the rising and falling edges of the clock, for selecting one of the first and second bus access modes for each data transfer.
In the data processing apparatus, the first bus access mode of a single-edge type and the second bus access mode of a double-edge type can selectively be used in a data transfer cycle executed on the same bus. Since, in the double-edge type bus access mode, data is transferred at two times the speed in the single-edge type bus access mode, the transfer bandwidth of data can be expanded. Particularly in the band-guaranteed cycle for transferring data in real time by assigning a reserved band for each cycle time, even though the time periods required for data transfer are the same, the bandwidth of stream data can be expanded substantially two times using the second bus access mode of the double-edge type. It is thus possible to efficiently transfer stream data such as audio/video data in real time.
Since, furthermore, a bus access mode can be selected for each data transfer, data transfer between nodes can be performed in the second bus access mode of the double-edge type and data transfer between other nodes can be done in the first bus access mode of the single-edge type. If the performance of the sender node and that of the receiver node both correspond to the second bus access mode of the double-edge type, data can be transferred at high speed between the sender and receiver nodes in the second bus access mode of the double-edge type. Whether each of the nodes corresponds to the second bus access mode can be determined on the basis of performance information previously stored in the nodes.
If, as described above, the single edge and double edge can be switched by the performance of each of the sender and receiver nodes, the performance of the nodes can be delivered sufficiently. Since, moreover, a circuit for the double-edge transfer has only to be incorporated into a node only for processing necessary stream data of a wide band, an internal circuit can be simplified in a node for processing relatively-low band data, thus decreasing in costs.
A data processing apparatus according to a second aspect of the present invention, comprises a bus for which a band-guaranteed cycle capable of transferring stream data in real time by assigning a predetermined reserved band for each cycle time and an asynchronous transfer cycle for asynchronously performing a transfer cycle during a period other than the reserved band by a bus access request of a bus master are each defined as a data transfer cycle; a plurality of nodes connected to the bus and capable of performing the data transfer cycle using one of the band-guaranteed cycle and the asynchronous transfer cycle; means for assigning one of plurality of channel numbers to a sender node and a receiver node of each stream data such that the stream data is transferred, using the band-guaranteed cycle in a peer-to-peer mode, between nodes to which a same channel number is assigned; and mode selection means having a first bus access mode for transferring the stream data in synchronization with one of rising and falling edges of a clock and a second bus access mode for transferring the stream data in synchronization with each of the rising and falling edges of the clock, for selecting one of the first and second bus access modes for each channel number to transfer the stream data using the band-guaranteed cycle.
The above data processing apparatus has both the band-guaranteed cycle and asynchronous transfer cycle. If the band-guaranteed cycle is used for transfer of stream data and the asynchronous transfer cycle is used for transfer of other data, both the AV stream and computer data can be transferred sufficiently on the same bus. It is thus possible to achieve both the band guarantee of AV stream and a high-speed response to an event caused asynchronously. In the band-guaranteed cycle, the same channel number is assigned to the sender and receiver nodes and thus a logical peer-t
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Vo T. M
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