Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-09-08
2001-03-06
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06199184
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a signature analyzer circuit for fault detection in electronic circuits, and more particularly to a signature compression circuit that latches test outputs from an electronic circuit under test and compresses them in parallel.
BACKGROUND OF THE INVENTION
U.S. Pat. No. 5,051,996 issued to Bergeson et al. on Sep. 24, 1991 teaches the overall test methodology of testing semiconductor integrated circuit devices, all of whose disclosures are incorporated herein by reference. If component level isolation of fault is desired, the serial signature technique is appropriate. However, if all that are required is fault detection, the parallel technique is the appropriate choice.
In signature analysis, either the parallel or serial signature analyzer is utilized. For signature compression, a multiple input signature register (MISR) is incorporated in the parallel signature analyzer (PSA) while a single input signature register (SISR) is incorporated in the serial signature analyzer (SSA). Considering signature analyzer area, the parallel compression technique utilizing the MISR is more profitable than the serial compression technique utilizing the SISR; the former requires only one MISR but the latter requires a plurality of SISRs. Therefore, recently, the parallel signature compression method is widely used for effectively analyzing signatures.
FIG. 1
is a view schematically illustrating a parallel signature compression technique, which is usually employed to analyze high speed semiconductor integrated circuits. As shown in
FIG. 1
, a semiconductor integrated circuit
10
, such as a microprocessor, a RAM (random access memory), a ROM (read only memory), or a PLA (programmable logic array), is tested. A test input pattern is given to the circuit under test
10
which provides test outputs (i.e., response data) to a compression circuit
12
(i.e., MISR). The test outputs are compressed in the compression circuit
12
in parallel. At the end of the test, a signature (resultant data) of the test is stored in the compression circuit
12
. signature of the test which is generated by compressing the test outputs is read out of the compression circuit
12
, and then the externally read contents are compared with expected values. Based on the comparison, the integrated circuit
10
is analyzed.
As described in “Testing Semiconductor Memories”, by John Wiley & Sons, 1991, pp. 204-209, the signature generated by compressing a test output pattern with errors can be identical with the signature generated by compressing a test output pattern with no error. Namely, there can take place a masking of the signature obtained by compressing the erroneous pattern. The term “masking” defines that an erroneous test output pattern maps into the same signature as the good test outputs.
If the length of the pattern sequences outputted from the circuit under test is longer than the bit length n of the signature register and if respective patterns have the same error generation probability, it is generally known in the art that the probability of masking is ½
n
. However, since the above assumption is impracticable, it is required to pay more attention to applying the probability, depending on applications.
The MISR can be implemented in a software or hardware form. In particular, the hardware MISR is a major component of the built-in self test circuit for VLSI logics and memories.
FIG. 2
illustrates a typical MISR for compressing the response data of a circuit under test in parallel. As seen in the figure, MISR
20
includes 6 flip-flop circuits (hereinafter referred to as F—F circuits)
21
-
1
,
21
-
2
, . . . , and
21
-
6
corresponding to a 6-bit test output pattern P
1
-P
6
, respectively. Each F—F circuit
21
-i is coupled to the next F—F circuit
21
-(i+1) on the upper bit side via an exclusive OR (XOR) gate
23
-(i+1), where i=1, 2, . . . , or 6. One XOR gate
23
-i and one F—F circuit
21
-i constitute a cell. The MISR
20
further includes a feedback tap
25
. This tap
25
is coupled to an input of XOR gate
27
whose the other input is coupled to the output of the F—F circuit
21
-
5
. The output of the XOR gate
27
is applied to an input of XOR gate
23
-
1
in the lowest bit position.
Another structure of MISR is illustrated in FIG.
3
. MISR
30
has the same circuit construction as the MISR
20
of
FIG. 2
, except for having a different feedback tap.
In MISR, if there are errors repetitively on the pattern sequence from a circuit under test, i.e., if MISR is used in compressing the repetitive error patterns, masking can take place. The term “repetitive error patterns” means that in two arbitrary patterns on the pattern sequence, errors are generated at the same interval as the distance between the two patterns. The repetitive error patterns have an odd-numbered distance or even-numbered distance according to the distance between the two patterns.
Repetitive error patterns with distance of 3 and repetitive error patterns with distance 4 are shown in Tables 1 and 2, respectively.
TABLE 1
Bit Positon
P1
P2
P3
P4
P5
P6
Pattern
1
0
0
0
0
0
Sequence
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
TABLE 2
Bit Positon
P1
P2
P3
P4
P5
P6
Pattern
1
0
0
0
0
0
Sequence
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
In the Tables 1 and 2, each row represents a test output pattern. In each pattern, a good data bit is represented by “0” and an erroneous data bit by “1”.
In Table 1, after an error appears in the first bit position P
1
of the first error pattern of “100000”, a repetitive error happens in the fourth bit position of the second error patter of “000100”. Namely, the interval between the erroneous bit P
1
of the first error pattern 100000 and the erroneous bit P
4
of the second error pattern 000100 is equal to the instance between the first and second patterns (i.e., 3). Like this, in Table 2, the interval between the erroneous bit P
1
of the first error pattern 100000 and the erroneous bit P
5
of the second error pattern 000010 is equal to the instance between the first and second patterns (i.e., 4).
Table 3 shows the resultant data (i.e., signature) obtained by compressing the repetitive error patterns of Table 1 by means of the MISR
20
of FIG.
2
.
TABLE 3
Signature
S1
S2
S3
S4
S5
S6
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
As shown in Table 3, during the compression of first through third patterns, the erroneous bit P
1
of the first error pattern 100000 in Table 1 is shifted twice. However, during the compression of the second error pattern 000100, it can be seen that the error effect is not propagated to the fourth F—F circuit
21
-
4
of FIG.
2
. Namely, when the second error pattern 000100 is inputted to the MISR
20
, its fourth signature bit S
4
is “0”. This means that the masking occurs. As a result, neither of error effects of the two error patterns is transferred to the signature Sout.
Table 4 shows the signature obtained by compressing the repetitive error patterns of Table 2 by means of the MISR
20
of FIG.
2
.
TABLE 4
Signature
S1
S2
S3
S4
S5
S6
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
As seen in Table 4, during the compression of first through fourth patterns, the erroneous bit P
1
of the first error pattern 100000 in Table 1 is shifted three times. Also, during the compression of the second error pattern 000010, the error effect is not propagated to the fourth F—F circuit
21
-
5
of
FIG. 2
, so that the fifth signature bit S
5
is “0”. Due to this masking, neither of error effects of the two error patterns is also transferred to the signature Sout.
The above described repetitive error patterns may be easily found during memory fault detection. Therefore, it is required to consider the repetitive error patterns as an important input class of the MISRs used in testing integrated circuit memories.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a parallel signature compression register circuit with an improved error masking probability.
It is anoth
Cady Albert De
Chase Shelly A
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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