Parallel bit test circuits for testing semiconductor memory...

Details Parallel bit test circuits for testing semiconductor memory... Parallel bit test circuits for testing semiconductor memory...

2006-08-07

2009-02-03

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S030000, C714S048000

Reexamination Certificate

active

07487414

ABSTRACT:
An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first and second memory banks. The test circuit is further configured to merge respective ones of the first set of test results with respective ones of the second set of test results to provide a set of merged test results to respective ones of a set of output terminals of the integrated circuit device. The at least one flag generator circuit is configured to generate a first flag signal that indicates a presence of at least one memory test error in the first set of test results, and a second flag signal that indicates a presence of at least one memory test error in the second set of test results. Based on the set of merged test results and the first and second flag signals, the test circuit may determine which of the memory blocks of the first and second memory banks includes a defective memory cell therein. Related methods are also discussed.

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