Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-28
2009-12-01
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000, C714S724000, C714S733000, C714S734000, C345S050000, C345S053000, C345S204000, C345S213000, C348S181000, C348S766000, C348S184000, C348S180000
Reexamination Certificate
active
07627799
ABSTRACT:
A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.
REFERENCES:
patent: 4513318 (1985-04-01), Wilensky et al.
patent: 5448260 (1995-09-01), Zenda et al.
patent: 5502511 (1996-03-01), Nagel
patent: 5668594 (1997-09-01), Cahill, III
patent: 5696540 (1997-12-01), Katsura et al.
patent: 6292182 (2001-09-01), Park et al.
patent: 6784881 (2004-08-01), Wasserman et al.
patent: 6862021 (2005-03-01), Kudo et al.
patent: 6917215 (2005-07-01), Ichikawa
patent: 7143326 (2006-11-01), Fan et al.
patent: 7486334 (2009-02-01), Masuda et al.
patent: 2003/0137587 (2003-07-01), Braun
patent: 0501377 (1992-09-01), None
patent: 05265393 (1993-10-01), None
patent: 10069257 (1998-03-01), None
patent: 10274957 (1998-10-01), None
patent: 2001296507 (2001-10-01), None
patent: P1999-0006216 (1999-01-01), None
patent: 2000 0260362 (2000-04-01), None
patent: 2003 0024414 (2003-03-01), None
patent: 102001005755 (2003-03-01), None
Japanese Translation of Patent Application Publication JP10274957 A, 8 pages, 3 PDF files.
Kang Won-Sik
Lee Jae-Goo
F. Chau & Associates LLC
Samsung Electronics Co,. Ltd.
Trimmings John P
LandOfFree
Panel driving circuit that generates panel test pattern and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Panel driving circuit that generates panel test pattern and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Panel driving circuit that generates panel test pattern and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4094623