Packet buffer circuit and method

Details Packet buffer circuit and method Packet buffer circuit and method

2005-04-26

2005-04-26

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189011, C365S189070

Reexamination Certificate

active

06885591

ABSTRACT:
A method and circuit buffer for temporarily holding packets of information. The buffer may include a first memory and a second memory for holding the packets of information. The first memory may be a read-once memory in which data stored in the first memory is destroyed upon being read therefrom the first time. The second memory may be a memory in which stored data therein is not destroyed following the data being read from the second memory the first time. The buffer includes at least one queue. The head-of-line packet of the at least one queue is stored in the second memory. Incoming fanout splitting packets are stored in the second memory and other incoming packets are initially stored in the first memory.

REFERENCES:
patent: 5926424 (1999-07-01), Abe
Iyer, et al., “Analysis of a Memory Architecture for Fast Packet Buffers”, In Proc. IEEE HPSR, Dallas, Texas, pp. 368-373; 2001, 7803-6711-1/01.
Mike Clendenin; “IBM shows faster approach to embedded DRAM”, EE Times, Jun. 10, 2002. URL: htttp://www.embedded.com/showArticle.jhtml?articleID=10804520.

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