Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-10-19
2003-12-30
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S743000
Reexamination Certificate
active
06671845
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to a system for testing memory devices.
RELATED ART
It is well known to use a test system to test the reliability of a semiconductor device, such as a conventional dynamic random access memory (DRAM) or static random access memory (SRAM). The conventional test system typically provides a test signal pattern (so called “test vector”) to a semiconductor device under test (“DUT”) and compares an output signal from the DUT with an expected signal to determine whether the DUT functions correctly. For exemplary test systems, see, for example, U.S. Pat. No. 5,946,247 to Osawa et al.; U.S. Pat. No. 4,862,460 to Yamaguchi; and U.S. Pat. No. 4,502,127 to Garcia et al, which are incorporated herein by reference in their entirety.
Recently introduced memory devices, such as Direct RDRAM™ from RAMBUS of Mountain View, Calif., use variably time spaced, “packet” based address and data communications. A “packet” includes multiple “streams” transmitted in parallel, where each stream is 8 serial ordered bits. For a description of Direct RDRAM™, see the Direct RDRAM™ Datasheet available from RAMBUS, which is incorporated by reference herein in its entirety. Herein, “Direct RDRAM™” means any device compatible with the Direct RDRAM™ such as Synclink. Such address and data packet communications further include interspersed instructions. Thus, to test such recent memory systems, a test system must provide such variably time spaced and instruction-interspersed, packet based communications.
FIG. 1A
depicts in a block diagram form a Direct RDRAM™ device
100
. Direct RDRAM™ device
100
includes distinct terminals labeled ROW, COLUMN, DATA
0
, and DATAl. Commands “ROWA” and “ROWR” are input to terminal ROW. Commands “COLC/M” and “COLC/X” are input to terminal COLUMN. Commands “DQA” and “DQB” are input to respective terminals DATA
0
and DATA
1
. Direct RDRAM™ uses the packet-based commands “ROWA” and “ROWR” for row identification, “COLC/M” and “COLC/X” for column identification, and a combination of. “DQA” and “DQB” for data specification.
FIG. 1B
depicts the bit designations of commands “ROWA”, “ROWR”, “COLC”, “COLX” and “COLM”. Command “COLC/X” is a combination of commands “COLC” and “COLX” whereas “COLC/M” is a combination of commands “COLC ” and “COLM”. Commands “ROWA” and “ROWR” each include three streams (numbered 0 to 2), each stream being 8 bits in serial order. As shown, command “ROWA” includes bits “DR
4
T”, “DR
4
F”, “DR
0
” to “DR
3
”, “BR
0
” to “BR
3
”, 2 bits of “RsvB”, 2 bits of “RsvR”, “AV”, and “R
0
” to “R
8
”. Direct RDRAM™ defines “DR
4
T” and “DR
4
F” as bits for framing (recognizing) a “ROWA” or “ROWR” command; “DR
0
” to “DR
3
”, “DR
4
T”, and “DR
4
F” as a device address for “ROWA” and “ROWR” commands; “BR
0
” to “BR
3
” as a bank address for “ROWA” and “ROWR” commands; “AV” as a bit for selecting between “ROWA” and “ROWR” commands; and “R
0
” to “R
8
” as a row address for the “ROWA” and “ROWR” commands. The two bits of “RsvB” are reserved for future bank address extensions whereas the two bits of “RsvR” are reserved for future row address extensions.
Command “ROWR” is used to precharge address specified memory cells, which will be accessed subsequently. The bit designations of command “ROWR” are the same as those of command “ROWA” except bit AV is 0.
As shown in
FIG. 1B
, command “COLC” includes bits “S”, “DC
0
” to “DC
4
”, “C
0
” to “C
5
”, “RsvC”, “BC
0
” to “BC
3
”, 2 bits of “RsvB”, and “COP
0
” to “COP
3
”. Direct RDRAM™ defines “S” as a bit for framing (recognizing) the “COLC” command; “DC
0
” to “DC
4
” as a device address for the “COLC” command; “C
0
” to “C
5
” as a column address for the “COLC” command; “RsvC” as a bit reserved for future expansion of the column address; “BCO” to “BC
3
” as a bank address for the “COLC” command; 2 bits of “RsvB” as bits reserved for future expansion of the bank address; and “COPO” to “COP
3
” as used to specify read, write, precharge, and power management functions.
As shown in
FIG. 1B
, command “COLC” includes undefined bits, shown as asterisk. Commands “COLX” and “COLM” are inserted into the undefined bits of command “COLC” to form respective commands “COLC/X” and “COLC/M”. Commands “COLC/X” and “COLC/M” each include five streams (numbered
0
to
4
), each being 8 bits in serial order.
Command “COLC/X” is used to specify an independent precharge command and for housekeeping and power management. Command “COLC/X” includes bits “M”, “DX
0
” to “DX
4
”, “XOP
0
” to “XOP
4
”, “BX
0
” to “BX
3
”, and 2 “RsvB” bits. Direct RDRAM™ defines “M=
0
” as identifying the “COLC/X” command; “DX
0
” to “DX
4
” as specifying the device address for the “COLC/X” command; “XOP
0
” to “XOP
4
” as an opcode field for the “COLC/X” command to specify precharge and power management functions; “BX
0
” to “BX
3
” as a bank address for the “COLC/X” command; and the 2 “RsvB” bits as reserved for expansion of the bank address.
Command “COLC/M” is used to specify byte mask control. Command “COLC/M” includes bits “M”, “MA
0
” to “MA
7
”, and “MB
0
” to “MB
7
”. Direct RDRAM™ defines “M=
1
” as identifying the “COLC/M” command; “MA
0
” to “MA
7
” as byte mask write control bits; and “MB
0
” to “MB
7
” as byte mask write control bits.
Direct RDRAM™ defines data commands “DQA” and “DQB” each as nine streams (numbered
0
to
8
), each stream including 8 bits in serial order. Commands “DQA” and “DQB” include only data.
FIG. 1C
schematically depicts an exemplary sequence of packet-based commands “ROWA”, “ROWR”, “COLC/M”, “COLC/X”, “DQA”, and “DQB”. The time spacing between the start and ending of sequential, packet-based commands is variable.
One conventional test system uses multiple accelerated APGs (algorithmic pattern generators) to generate address and data commands at a rate required by a Direct RDRAM™ compatible DUT. For descriptions of exemplary APGs, see U.S. Pat. No. 5,946,247 to Osawa et al.; U.S. Pat. No. 4,862,460 to Yamaguchi; and U.S. Pat. No. 4,502,127 to Garcia et al, which are incorporated by reference herein in their entirety. However, such accelerated APGs are expensive. Further, complex logic circuitry is required to form commands from the address and data from the multiple APGs thereby making the test system difficult for a tester to use.
Thus what is needed is a test system that provides variably time spaced, packet based communications to test DUTs without use of multiple accelerated APGs.
SUMMARY
An embodiment of the present invention includes a packet generator that generates packet-based address and data commands to a device under test (DUT). In one embodiment, the packet generator receives column and row addresses and data from a single conventional (non-accelerated) algorithmic pattern generator (APG) and generates column and row addresses and data in packet form, thereby allowing communications with a packet-based device, such as a memory system. The packet generator further provides variable time spacing between column and row addresses and data packets without modification of a conventional timing and formatting circuitry. Thereby, the packet generator advantageously allows testing of memory DUTs that require signal inputs at a higher rate than a conventional APG can provide.
Thereby an embodiment of the present invention includes a method of providing packet-based address and data commands to a device under test (DUT), the method including the acts of: providing a data at a data rate; providing addresses at an address rate; providing user-specified instructions; providing to the DUT address packets that include the addresses and the user-specified instructions at a rate faster than the address rate; and providing to the DUT data packets that include the data and the user-specified instructions at a rate faster than the data rate.
REFERENCES:
patent: 4165092 (1979-08-01), Herlein
patent: 4502127 (1985-02-01), Garcia et al.
patent: 4511846 (1985-04-01), Nagy et al.
patent: 4635256 (1987-01-01), Herlein
patent: 4675562 (1987-06-01), Herlein
patent: 4789835
Dorsey & Whitney LLP
Schlumberger Technologies Inc.
Ton David
Torres Joseph D.
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