Overlay process for fabricating a semiconductor device

Details Overlay process for fabricating a semiconductor device Overlay process for fabricating a semiconductor device

1999-02-03

2001-05-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

06228705

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and, more particularly, to a process for fabricating such devices that tightly controls overlay among the masks used in conjunction with photolithographic equipment.
BACKGROUND OF THE INVENTION
Semiconductor devices are typically constructed with a plurality of layers or levels, each of which are selectively deposited and etched to fabricate the device. The etching processes are typically controlled with masks used in conjunction with photolithographic equipment. Each layer is formed by an individual deposition and etching process, and the device is fabricated by building successive layers of the device from the bottom up. The etching process corresponding to each layer is governed by a separate mask, which controls how that layer is etched and formed. For the finished device to work properly, and to maximize the efficiency of the fabrication process, the masks that govern the formation of the various layers must be aligned precisely so that the various layers of the device align, or register, properly.
In conventional processes for fabricating a semiconductor device, a given layer of the device is aligned with only the immediately previous layer of the device. The given layer is not aligned with the layer under the immediately previous layer (a “second-previous” layer). Typically, this alignment approach results both in first-order alignment error between the given layer and the previous layer and in second-order alignment error between the given layer and the second-previous layer. Accordingly, as the various layers are fabricated to form the device, these second-order alignment errors between layers can accumulate, causing the overlay among the various layers to deteriorate and leading to overall process inefficiency and possible device failure. The accumulated alignment error can be reduced, however, if the alignment error between the given layer and the second-previous layer is reduced to first-order. Conventional fabrication processes do not provide first-order alignment error between the given layer and both of the two previous layers.
As the size of semiconductor devices continues to decrease, the registration between the various layers of those devices becomes more critical. Accordingly, there exists a need in the art for fabrication processes that provide the tightest possible registration between those various layers, preferably with first-order alignment error between a given layer and both of the two previous layers.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a process for fabricating a semiconductor device comprising the following steps. In an exemplary embodiment of the invention, the process defines a first registration mark associated with a first mask level of the semiconductor device, and defines a second registration mark associated with a second mask level of the semiconductor device. The process then aligns a third mask level of the semiconductor device based on the first and second registration marks. Specifically, the process aligns the third mask level along a first axis with respect to the first registration mark, and aligns the third mask level along a second axis with respect to the second registration mark. According to various aspects of the invention, the semiconductor fabrication process is used to fabricate dynamic random access memory (DRAM) trench cells, or any other type of semiconductor device whose fabrication requires tight overlay alignment between the various levels of the device. The process of the invention is generally applicable to any semiconductor fabrication process that requires alignment of a third mask at an intersection point of two alignment marks associated with two previous levels.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


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